Nanosheet capacitor

Patent metadata

Field	Value
Publication number	US-10157935-B2
Application number	US-201715439417-A
Country	US
Kind code	B2
Filing date	Feb 22, 2017
Priority date	Sep 22, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a nanosheet capacitor by forming a first nanosheet stack over a substrate. The first nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A second nanosheet stack is formed over the substrate adjacent to the first nanosheet stack. The second nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. Exposed portions of the first and second nanosheets of the second nanosheet stack are doped and gates are formed over channel regions of the first and second nanosheet stacks.

First claim

What is claimed is:

1. A semiconductor device comprising:
a nanosheet capacitor adjacent to a nanosheet field effect transistor, the nanosheet capacitor comprising:
a nanosheet stack formed over a substrate, the nanosheet stack comprising a first nanosheet vertically stacked over a second nanosheet, the first and the second nanosheet comprising a same semiconductor material;
a first source or drain region adjacent to a first end of the nanosheet stack;
a second source or drain region adjacent to a second end of the nanosheet stack, the first and second ends on opposite sides of the nanosheet stack;
a dopant formed in a channel region of the first and second nanosheets of the nanosheet stack; and
a gate formed over the channel region of the first and second nanosheets of the nanosheet stack, the gate wrapping around the channel region of each of the first and second nanosheets and filling a gap between the first and second nanosheets;
wherein the first source or drain region, the second source or drain region, and the first and second nanosheets comprise a same doping type; and
wherein the first and second nanosheets are doped such that the first and second nanosheets act as a single electrode between the first and second source or drain regions.

2. The semiconductor device of claim 1 , wherein the first and second source or drain regions are n-type doped regions and the dopant comprises an n-type dopant.

3. The semiconductor device of claim 2 , wherein the n-type dopant is selected from the group consisting of phosphorus and arsenic.

4. The semiconductor device of claim 1 , wherein the first and second source or drain regions are p-type doped regions and the dopant comprises a p-type dopant.

5. The semiconductor device of claim 4 , wherein the p-type dopant is selected from the group consisting of boron and gallium.

6. The semiconductor device of claim 1 , wherein each nanosheet of the nanosheet stack has a thickness of about 4 nm to about 10 nm.

7. The semiconductor device of claim 1 , wherein each nanosheet of the nanosheet stack has a thickness of about 6 nm.

8. The semiconductor device of claim 1 , wherein a concentration of the dopant formed in the channel region of the first and second nanosheets of the nanosheet stack is about 1×10 19 cm −3 to about 2×10 21 cm −3 .

9. The semiconductor device of claim 1 , wherein a concentration of the dopant formed in the channel region of the first and second nanosheets of the nanosheet stack is about 1×10 20 cm −3 to about 1×10 21 cm −3 .

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao
• Wang Geng
• Zhang Qintao

Classifications

• H01L29/0665

  Electricity · mapped topic

• H01L29/423

  Electricity · mapped topic

• H01L27/1211 Primary

  Electricity · mapped topic

• H01L29/778

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic