Eliminate sawing-induced peeling through forming trenches

US9589903B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9589903-B2
Application numberUS-201514713935-A
CountryUS
Kind codeB2
Filing dateMay 15, 2015
Priority dateMar 16, 2015
Publication dateMar 7, 2017
Grant dateMar 7, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die, and a bottom dielectric layer over the device die and the molding material. A plurality of redistribution lines (RDLs) extends into the bottom dielectric layer and electrically coupling to the device die. A top polymer layer is over the bottom dielectric layer, with a trench ring penetrating through the top polymer layer. The trench ring is adjacent to edges of the package. The package further includes Under-Bump Metallurgies (UBMs) extending into the top polymer layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A package comprising: a device die; a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die; a bottom dielectric layer over the device die and the molding material; a plurality of redistribution lines (RDLs) extending into the bottom dielectric layer and electrically coupling to the device die; a top polymer layer over the bottom dielectric layer; an intermediate polymer layer between the top polymer layer and the bottom dielectric layer, with a trench ring penetrating through the intermediate polymer layer, wherein the trench ring is adjacent to edges of the package, and the trench ring is filled by the top polymer layer; and Under-Bump Metallurgies (UBMs) extending into the top polymer layer. 2. The package of claim 1 , wherein the trench ring is spaced apart from edges of the package by a portion of the intermediate polymer layer, with the portion of the intermediate polymer layer forming a ring encircling the trench ring. 3. The package of claim 1 , wherein the trench ring extends to edges of the package. 4. The package of claim 1 , wherein the trench ring extends to a top surface of the bottom dielectric layer. 5. The package of claim 1 , wherein the trench ring is fully filled by the top polymer layer. 6. The package of claim 1 , wherein the trench ring is partially filled by the top polymer layer. 7. The package of claim 1 further comprising a through-via penetrating through the molding material, wherein a top surface of the through-via is substantially coplanar with the top surface of the device die. 8. The package of claim 1 further comprising an additional trench ring penetrating through the top polymer layer, wherein the additional trench ring is adjacent to edges of the package. 9. The package of claim 1 further comprising a plurality of openings in the intermediate polymer layer, with some of the plurality of RDLs extending into the plurality of openings, wherein the trench ring is formed simultaneously as the plurality of openings. 10. A package comprising: a device die; a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die; a through-via penetrating through the molding material, wherein a top surface of the through-via is substantially coplanar with the top surface of the device die; a first polymer layer over and in contact with the device die, the through via, and the molding material; a plurality of redistribution lines (RDLs) extending into the first polymer layer to electrically couple to the device die and the through-via; a second polymer layer over the first polymer layer and the plurality of RDLs, wherein a first trench ring extends from a top surface of the second polymer layer to a top surface of the first polymer layer; a third polymer layer over and in contact with the second polymer layer, wherein a second trench ring extends from a top surface of the third polymer layer to a top surface of the second polymer layer; and Under-Bump Metallurgies (UBMs) extending into the third polymer layer. 11. The package of claim 10 , wherein the first trench ring is between the second trench ring and edges of the package. 12. The package of claim 10 , wherein the first trench ring stops on a top surface of the first polymer layer, and the second trench ring stops on a top surface of the second polymer layer. 13. The package of claim 10 , wherein the first trench ring is filled by the third polymer layer. 14. A method comprising: molding a plurality of device dies in a molding material; planarizing the plurality of device dies and the molding material, wherein top surfaces of the device dies are level with a top surface of the molding material; forming a first polymer layer over and contacting the plurality of device dies and the molding material; patterning the first polymer layer to form a first plurality of openings, with metal pillars of the device dies exposed through the first plurality of openings, wherein scribe lines are formed by the patterning the first polymer layer; forming a plurality of redistribution lines comprising via portions penetrating through the first polymer layer; forming a second polymer layer over the first polymer layer; and patterning the second polymer layer to form a second plurality of openings and a first plurality of trench rings, with each of the first plurality of trench rings encircling one of the plurality of device dies, and the first plurality of trench rings is separated from each other by the scribe lines; and forming a plurality of Under-Bump Metallurgies (UBMs) extending into the second polymer layer. 15. The method of claim 14 further comprising sawing the first polymer layer, the second polymer layer, and the molding material along the scribe lines. 16. The method of claim 14 further comprising: after forming the first polymer layer and before forming the second polymer layer, forming a third polymer layer, with the second polymer layer being formed over the first polymer layer; and patterning the third polymer layer to form a third plurality of openings and a second plurality of trench rings, with each of the second plurality of trench rings encircling one of the plurality of device dies, and the second plurality of trench rings is separated from each other by the scribe lines. 17. The method of claim 16 , wherein the second polymer layer is filled into the second plurality of trench rings. 18. The method of claim 14 , wherein a plurality of through-vias is molded in the molding material, and wherein the plurality of redistribution lines is electrically connected to the plurality of through-vias. 19. The method of claim 14 , wherein the first plurality of trench rings is formed simultaneously as the second plurality of openings. 20. The method of claim 14 , wherein the first plurality of trench rings is formed using a photo lithography process.

Assignees

Inventors

Classifications

  • between stacked chips · CPC title

  • the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

  • batch processes · CPC title

  • Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

  • Die-attach connectors and bond wires · CPC title

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What does patent US9589903B2 cover?
A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die, and a bottom dielectric layer over the device die and the molding material. A plurality of redistribution lines (RDLs) extends into the bottom dielectric layer and electrically coupling to the device die. A top …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W74/117. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).