Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-10157751-B1
Application number	US-201715794262-A
Country	US
Kind code	B1
Filing date	Oct 26, 2017
Priority date	Oct 26, 2017
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A method for manufacturing a semiconductor device, including forming a first hard mask strip, a second hard mask strip, and a dummy structure over a substrate, in which the dummy structure is formed between and in contact with the first hard mask strip and the second hard mask strip; forming a hard mask layer over the first hard mask strip, the dummy structure, and the second hard mask strip; patterning the hard mask layer to form an opening exposing the first hard mask strip and the dummy structure, and partially exposing the second hard mask strip; and performing an etching process to remove the first hard mask strip and form a recess in the second hard mask strip, in which the performing the etching process includes forming a polymer in the recess.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a first hard mask strip, a second hard mask strip, and a dummy structure over a substrate, wherein the dummy structure is formed between and in contact with the first hard mask strip and the second hard mask strip;
forming a hard mask layer over the first hard mask strip, the dummy structure, and the second hard mask strip;
patterning the hard mask layer to form an opening exposing the first hard mask strip and the dummy structure, and partially exposing the second hard mask strip; and
after patterning the hard mask layer, performing an etching process to remove the first hard mask strip and form a recess in the second hard mask strip, wherein the performing the etching process comprises forming a polymer in the recess.

2. The method of claim 1 , wherein the polymer and the patterned hard mask layer cover the remained second hard mask strip during the etching process.

3. The method of claim 1 , wherein patterning the hard mask layer is such that a surface of the first hard mask strip exposed from the opening is larger than a surface of the second hard mask strip exposed from the opening.

4. The method of claim 1 , wherein performing the etching process further comprises tuning an amount of etchants to increase an amount of the polymer.

5. The method of claim 4 , wherein the etchants comprise CF 4 and O 2 , and performing the etching process further comprises tuning an amount of O 2 to increase the amount of the polymer.

6. The method of claim 4 , wherein the etchants comprises BCl 3 and H 2 , and performing the etching process further comprises tuning an amount of H 2 to increase the amount of the polymer.

7. The method of claim 4 , wherein the etchants comprises CF 4 and CH 4 , and performing the etching process further comprises tuning an amount of CH 4 to increase the amount of the polymer.

8. The method of claim 4 , wherein the etchants comprises NF 3 and CH 4 , and performing the etching process further comprises tuning an amount of CH 4 to increase the amount of the polymer.

9. The method of claim 1 , wherein the polymer is further formed on the patterned hard mask layer adjacent to the recess.

10. The method of claim 1 , wherein the polymer is further formed on the dummy structure adjacent to the recess.

11. A method for manufacturing a semiconductor device, comprising:
forming a mandrel structure over a substrate;
forming a first sidewall spacer and a second sidewall spacer respectively on opposite sidewalls of the mandrel structure;
forming a patterned mask over the substrate and exposing the first sidewall spacer, the second sidewall spacer, and the mandrel structure; and
after forming the patterned mask, performing an etching process to remove the first sidewall spacer and form a first recess in the second sidewall spacer, wherein the performing the etching process comprises forming a polymer in the first recess.

12. The method of claim 11 , wherein a second recess is formed by removing the first sidewall spacer, and the second recess is deeper than the first recess in the second sidewall spacer.

13. The method of claim 12 , wherein the polymer is partially formed in the second recess.

14. The method of claim 11 , further comprising tuning a concentration of etchant gases of the etching process to increase an amount of the polymer.

15. A method for manufacturing a semiconductor device, comprising:
forming a first dummy structure over a substrate;
forming a first hard mask strip and a second hard mask strip over the substrate, wherein the first dummy structure is between the first and second hard mask strips;
after forming the first and second hard mask strips, forming a patterned mask over the substrate and partially exposing the second hard mask strip; and
after forming the patterned mask, performing an etching process to remove the first hard mask strip and form a recess in the second hard mask strip, wherein the performing the etching process comprises forming a polymer in the recess.

16. The method of claim 15 , further comprising:
removing the patterned mask; and
after removing the patterned mask, patterning the substrate using the first hard mask strip and the second hard mask strip as masks to form a plurality of fins thereon.

17. The method of claim 16 , further comprising removing the polymer prior to pattering the substrate.

18. The method of claim 15 , further comprising forming a second dummy structure alongside the first hard mask strip prior to forming the patterned mask, wherein the first dummy structure and the second dummy structure are made of the same material.

19. The method of claim 15 , wherein forming the first hard mask strip and the second hard mask strip is performed such that a third hard mask strip is formed parallel with the first and second hard mask strips, wherein the third hard mask strip is protected by the patterned mask during performing the etching process.

20. The method of claim 15 , wherein the recess in the second hard mask strip is filled with the polymer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Jung-Hao
• Huang Chao-Hsien
• Lan Wen-Ting
• Ju Shi-Ning
• Lin Li-Te
• Ching Kuo-Cheng

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H01L29/66795

  Electricity · mapped topic

• H01L21/0337

  Electricity · mapped topic