Gate protection circuit and display device including the same
US-9984641-B2 · May 29, 2018 · US
US10157567B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10157567-B2 |
| Application number | US-201715476133-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 31, 2017 |
| Priority date | Jul 11, 2016 |
| Publication date | Dec 18, 2018 |
| Grant date | Dec 18, 2018 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A display apparatus includes a display panel, a gate driver, and a gate driving control circuit. The gate driver is connected to the display panel, and generates gate signals for driving the display panel using a gate clock signal. The gate driving control circuit generates the gate clock signal using a gate on voltage and a gate off voltage, determines whether an operation environment is an abnormal temperature environment by comparing a first feedback gate signal with a second feedback gate signal, and adjusts a voltage level of the gate clock signal in the abnormal temperature environment. The first feedback gate signal is retrieved from the display panel while a first frame image is displayed on the display panel. The second feedback gate signal is retrieved from the display panel while a second frame image subsequent to the first frame image is displayed on the display panel.
Opening claim text (preview).
What is claimed is: 1. A display apparatus comprising: a display panel; a gate driver circuit connected to the display panel, and configured to generate a plurality of gate signals for driving the display panel using a gate clock signal; and a gate driving control circuit configured to generate the gate clock signal using a gate on voltage and a gate off voltage, configured to determine whether an operation environment is a normal environment or an abnormal temperature environment by comparing a first feedback gate signal with a second feedback gate signal, and configured to adjust a voltage level of the gate clock signal when it is determined that the operation environment is the abnormal temperature environment, wherein the first feedback gate signal is retrieved from the display panel while a first frame image is displayed on the display panel, and the second feedback gate signal is retrieved from the display panel while a second frame image subsequent to the first frame image is displayed on the display panel. 2. The display apparatus of claim 1 , wherein the gate driving control circuit is configured to: compare a first voltage value with a second voltage value; and determine that the operation environment is the abnormal temperature environment when a difference between the first and second voltage values is greater than a reference value, and wherein the first voltage value is a voltage difference between a high level and a low level of the first feedback gate signal, and the second voltage value is a voltage difference between a high level and a low level of the second feedback gate signal. 3. The display apparatus of claim 2 , wherein the gate driving control circuit is configured to: determine that the abnormal temperature environment is a low temperature environment when the first voltage value is greater than the second voltage value; and increase a high voltage level of the gate clock signal in the low temperature environment. 4. The display apparatus of claim 3 , wherein, in the low temperature environment, the gate driving control circuit is configured to increase the high voltage level of the gate clock signal by the difference between the first and second voltage values. 5. The display apparatus of claim 3 , wherein, in the low temperature environment, the gate driving control circuit is configured to: increase a level of the gate on voltage by the difference between the first and second voltage values; and increase the high voltage level of the gate clock signal using the increased gate on voltage. 6. The display apparatus of claim 2 , wherein the gate driving control circuit is configured to: determine that the abnormal temperature environment is a high temperature environment when the first voltage value is less than equal to the second voltage value; and decrease a high voltage level of the gate clock signal in the high temperature environment. 7. The display apparatus of claim 2 , wherein the gate driving control circuit comprises: a detector circuit configured to detect the first and second voltage values from the first and second feedback gate signals, respectively, and configured to store the first and second voltage values; a comparator circuit configured to generate a first comparison signal by comparing the difference between the first and second voltage values with the reference value, and configured to generate a second comparison signal by comparing the first voltage value with the second voltage value; and a gate clock generator circuit configured to generate the gate clock signal using the gate on voltage and the gate off voltage, and configured to adjust a high voltage level of the gate clock signal when it is determined, using the first and second comparison signals, that the operation environment is the abnormal temperature environment, and wherein the detector circuit, the comparator circuit, and the gate clock generator circuit are included in a single chip. 8. The display apparatus of claim 2 , wherein the gate driving control circuit comprises: a power management integrated circuit (PMIC) chip configured to generate the gate on voltage and the gate off voltage; and a gate dock generation integrated circuit (GCIC) chip configured to generate the gate clock signal using the gate on voltage and the gate off voltage, wherein the PMIC chip comprises: a detector configured to detect the first and second voltage values from the first and second feedback gate signals, respectively, and configured to store the first and second voltage values; a comparator configured to generate a first comparison signal by comparing the difference between the first and second voltage values with the reference value, and configured to generate a second comparison signal by comparing the first voltage value with the second voltage value; and a gate voltage level controller configured to generate the gate on voltage and the gate off voltage, and configured to adjust a level of the gate on voltage when it is determined, using the first and second comparison signals, that the operation environment is the abnormal temperature environment. 9. The display apparatus of claim 2 , wherein the gate driving control circuit comprises: a PMIC chip configured to generate the gate on voltage and the gate off voltage; and a GCIC chip configured to generate the gate clock signal using the gate on voltage and the gate off voltage, wherein the GCIC chip comprises: a detector configured to detect the first and second voltage values from the first and second feedback gate signals, respectively, and configured to store the first and second voltage values; a comparator configured to generate a first comparison signal by comparing the difference between the first and second voltage values with the reference value, and configured to generate a second comparison signal by comparing the first voltage value with the second voltage value; and a gate clock generator configured to generate the gate clock signal using the gate on voltage and the gate off voltage, and configured to adjust a high voltage level of the gate clock signal when it is determined, using the first and second comparison signals, that the operation environment is the abnormal temperature environment. 10. The display apparatus of claim 1 , further comprising: a plurality of gate lines connecting the display panel with the gate driver circuit, wherein the first and second feedback gate signals are retrieved from one of the plurality of gate lines. 11. The display apparatus of claim 10 , wherein the first and second feedback gate signals are retrieved from a first gate line among the plurality of gate lines, and among the plurality of gate lines, the first gate line is disposed closest to the gate driving control circuit. 12. The display apparatus of claim 10 , further comprising: a feedback line connecting the gate driving control circuit with a first gate line among the plurality of gate lines, wherein the first and second feedback gate signals are retrieved from the first gate line. 13. The display apparatus of claim 1 , further comprising; a plurality of gate lines and a dummy gate line connecting the display panel with the gate driver circuit, wherein the first and second feedback gate signals are retrieved from the dummy gate line. 14. The display apparatus of claim 1 , wherein the first and second frame images are two consecutive frame images displayed on the display panel. 15. The display apparatus of claim 1 , wherein the display panel comprises a display region including a plurality of pixels and a peri
Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title
Details of a shift registers arranged for use in a driving circuit · CPC title
Temperature compensation · CPC title
Details of voltage level shifters arranged for use in a driving circuit · CPC title
Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.