Gate protection circuit and display device including the same

Patent metadata

Field	Value
Publication number	US-9984641-B2
Application number	US-201615158471-A
Country	US
Kind code	B2
Filing date	May 18, 2016
Priority date	Aug 4, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A gate protection circuit includes: a clock signal generator to generate a plurality of gate clock signals; a gate driver to output gate signals based on the plurality of gate clock signals, the gate driver including a plurality of gate driving circuits cascaded to each other; and a monitoring line configured to transmit a feedback signal based on the plurality of gate clock signals via the plurality of gate driving circuits to the clock signal generator. The clock signal generator is to block generation of the plurality of gate clock signals in response to the feedback signal.

First claim

What is claimed is:

1. A gate protection circuit comprising:
a clock signal generator configured to generate a plurality of gate clock signals;
a gate driver configured to output gate signals based on the plurality of gate clock signals, the gate driver comprising a plurality of cascading gate driving circuits; and
a monitoring line configured to transmit a feedback signal based on the plurality of gate clock signals via the plurality of gate driving circuits to the clock signal generator,
wherein the clock signal generator is configured to block generation of the plurality of gate clock signals in response to the feedback signal,
wherein a plurality of gate clock lines corresponding to the plurality of gate clock signals are connected to the monitoring line.

2. The gate protection circuit of claim 1 , wherein each of the plurality of gate clock lines is connected to a diode configured to prevent reverse current.

3. The gate protection circuit of claim 2 , wherein the feedback signal comprises a voltage in which the plurality of gate clock signals overlap each other.

4. The gate protection circuit of claim 3 , wherein the gate clock signals have a same cycle and different phases.

5. The gate protection circuit of claim 4 , wherein the plurality of gate clock signals comprises n gate clock signals each configured to be phase-shifted by 1/nth of one cycle and to be output sequentially.

6. The gate protection circuit of claim 1 , wherein the clock signal generator is configured to block the generation of the plurality of gate clock signals when the feedback signal comprises a blank section or a low level.

7. The gate protection circuit of claim 6 , further comprising a timing controller configured to generate a plurality of gate generation signals to control the gate driver,
wherein the clock signal generator is configured to generate the plurality of gate clock signals in response to the plurality of gate generation signals.

8. The gate protection circuit of claim 7 , wherein the clock signal generator comprises:
a booster configured to boost the plurality of gate generation signals, and to output the plurality of gate clock signals;
an error detection circuit configured to detect whether the feedback signal is lower than a reference voltage;
a switching control circuit configured to output a switching-off control signal to block the generation of the plurality of gate clock signals when the feedback signal is lower than the reference voltage; and
a switcher configured to turn off transmission channels of the plurality of gate generation signals in response to the switching-off control signal.

9. A display device, comprising:
a display panel comprising a plurality of pixels configured to emit light in response to gate signals and data signals;
a data driver configured to output the data signals to the display panel;
a clock signal generator configured to generate a plurality of gate clock signals;
a gate driver comprising a plurality of gate driving circuits cascaded to each other, and configured to output the gate signals based on the plurality of gate clock signals; and
a monitoring line configured to transmit a feedback signal based on the plurality of gate clock signals via the plurality of gate driving circuits to the clock signal generator,
wherein the clock signal generator is configured to block generation of the plurality of gate clock signals in response to the feedback signal,
wherein a plurality of gate clock lines corresponding to the plurality of gate clock signals are connected to the monitoring line.

10. The display device of claim 9 , wherein the gate driver comprises a first gate driver at a side region of the display panel, and a second gate driver at another side region of the display panel.

11. The display device of claim 10 , wherein the monitoring line comprises a first monitoring line configured to transmit a first feedback signal from the first gate driver to the clock signal generator, and a second monitoring line configured to transmit a second feedback signal from the second gate driver to the clock signal generator.

12. The display device of claim 11 , wherein the first monitoring line is at the side region of the display panel, and
wherein the second monitoring line is at the other side region of the display panel.

13. The display device of claim 12 , wherein the clock signal generator is configured to block the generation of the plurality of gate clock signals when at least one of the first and second feedback signals comprises a blank section or a low level.

14. The display device of claim 13 , further comprising a timing controller configured to generate a plurality of gate generation signals to control the gate driver,
wherein the clock signal generator is configured to generate the plurality of gate clock signals in response to the plurality of gate generation signals.

15. The display device of claim 14 , wherein the clock signal generator comprises:
a booster configured to boost the plurality of gate generation signals, and to output the plurality of gate clock signals;
an error detection circuit configured to detect whether at least one of the first and second feedback signals is lower than a reference voltage;
a switching control circuit configured to output a switching-off control signal to block the generation of the plurality of gate clock signals when at least one of the first and second feedback signals is lower than the reference voltage; and
a switcher configured to turn off transmission channels of the plurality of gate generation signals in response to the switching-off control signal.

16. The display device of claim 15 , wherein the error detection circuit comprises:
an AND gate configured to receive the first and second feedback signals and to perform an AND operation; and
a comparator configured to compare an output voltage of the AND gate with the reference voltage.

17. The display device of claim 16 , wherein the switching control circuit is configured to output the switching-off control signal when the output voltage of the error detection circuit is at a low level.

18. The display device of claim 9 , wherein the display panel is an amorphous silicon gate (ASG) display panel.

Assignees

• Samsung Display Co Ltd

Inventors

• Kang Sung In
• Kim Kyun Ho
• Park Min Ho
• Jang Ji Eun

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title