Semiconductor memory devices and methods of operating the same

Patent metadata

Field	Value
Publication number	US-10156995-B2
Application number	US-201715398409-A
Country	US
Kind code	B2
Filing date	Jan 4, 2017
Priority date	Apr 26, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array including a plurality of bank arrays;
a control logic circuit configured to generate control signals by decoding a command from an external memory controller; and
an error correction circuit,
wherein the control logic circuit, during a write mode of the semiconductor memory device, is configured to control the error correction circuit to:
read a first unit of data from a selected sub page of a plurality of sub pages of a target page in the memory cell array, wherein the first unit of data comprises a first sub unit of data, a second sub unit of data and old parity data; and
generate first parity data based on one of the first sub unit of data and the second sub unit of data and main data to be written in the selected sub page while generating syndrome data by performing an error correction code (ECC) decoding on the first unit of data, and
wherein the error correction circuit, when the first sub unit of data includes at least one error bit, is configured to perform a selective modification on the first parity data based on a data mask signal associated with the main data,
wherein the selective modification comprises:
maintaining the first parity data when the main data is to be written into a memory location in which the first sub unit of data is stored; and
modifying the first parity data based on the syndrome data when the main data is to be written into a memory location in which the second sub unit of data is stored.

2. The semiconductor memory device of claim 1 , wherein
the error correction circuit is configured to perform a read operation on the first unit of data to correct the error bit and to perform a write operation on the main data within a column access strobe to column access strobe command delay time of the semiconductor memory device.

3. The semiconductor memory device of claim 1 , wherein the error correction circuit comprises:
a syndrome generation circuit configured to generate the syndrome data by performing the ECC decoding on the first unit of data;
a parity generator configured to generate the first parity data based on one of the first sub unit of data and the second sub unit of data and the main data; and
a conditional parity correction circuit configured to receive the syndrome data and the first parity data, and configured to selectively modify the first parity data based on the data mask signal to generate a second parity data.

4. The semiconductor memory device of claim 3 , wherein the syndrome generation circuit comprises:
a check bit generator configured to generate check bits based on the first sub unit of data and the second sub unit of data; and
a syndrome generator configured to generate the syndrome data based on the check bits and the old parity data.

5. The semiconductor memory device of claim 3 , wherein the conditional parity correction circuit comprises:
an exclusive OR gate configured to perform an exclusive OR on corresponding bits of the syndrome data and the first parity data during the write mode of the semiconductor memory device;
a parity controller configured to generate a selection signal based on a position of the error bit and a memory location in which the main data is to be written, wherein the position of the error bit is based on the syndrome data and the memory location is based on the data mask signal; and
a multiplexer configured to output one of the first parity data and an output of the exclusive OR gate as the second parity data, in response to the selection signal.

6. The semiconductor memory device of claim 5 , wherein when the position of the error bit is the same as the memory location in which the main data is to be written, the parity controller is configured to generate the selection signal such that the multiplexer outputs the first parity data as the second parity data.

7. The semiconductor memory device of claim 5 , wherein when the position of the error bit is different from the memory location in which the main data is to be written, the parity controller is configured to generate the selection signal such that the multiplexer outputs the output of the exclusive OR gate as the second parity data.

8. The semiconductor memory device of claim 5 , wherein the parity controller comprises:
a decoder configured to decode the syndrome data and the data mask signal to output a decoding signal indicating whether the position of the error bit is the same as the memory location in which the main data is to be written; and
a signal generator configured to generate the selection signal based on the decoding signal.

9. The semiconductor memory device of claim 1 , further comprising:
an ECC engine configured to generate a first partial parity data at least based on the main data, and
wherein the error correction circuit is configured to selectively determine whether to modify the first parity data further based on the first partial parity data.

10. The semiconductor memory device of claim 9 , wherein the error correction circuit comprises:
a syndrome generation circuit configured to generate the syndrome data by performing the ECC decoding on the first unit of data and configured to generate a second partial parity data based on a portion of the first unit of data; and
a conditional parity correction circuit configured to receive the syndrome data, the first partial parity data and the second partial parity data, and configured to selectively modify the first parity data based on the data mask signal to generate second parity data,
wherein the first parity data is generated based on the first partial parity data and the second partial parity data.

11. The semiconductor memory device of claim 10 , wherein the conditional parity correction circuit comprises:
a first exclusive OR gate configured to perform an exclusive OR on corresponding bits of the first partial parity data and the second partial parity data to generate the first parity data;
a second exclusive OR gate configured to perform an exclusive OR on corresponding bits of the syndrome data and the first parity data during the write mode of the semiconductor memory device;
a parity controller configured to generate a selection signal based on a position of the error bit and a memory location in which the main data to be written, wherein the position of the error bit is based on the syndrome data and the memory location is based on the data mask signal; and
a multiplexer configured to output one of the first parity data and an output of the second exclusive OR gate as the second parity data, in response to the selection signal.

12. The semiconductor memory device of claim 9 , wherein the ECC engine is disposed at a peripheral region of the semiconductor memory device and is shared by the error correction circuits.

13. A method of operating a semiconductor memory device including a memory cell array and an error correction circuit, the method comprising:
generating syndrome data based on a first unit of data read from a memory location corresponding to an address received from an external memory controller, wherein the first unit of data includes a first sub unit of data, a second sub unit of data and old parity data;
generating first parity data based on one of the first sub unit of data and the second sub unit of data and main data received from the memory controller; and
performing a selective modification on the first parity data when the first sub unit of data includes at least one error bit based on a data mask signal received from the memory controller,
wherein the selective modification comprises:
maintainin

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Sang-Uhn
• Chung Hoi-Ju
• Ryu Ye-Sin
• Cho Seong-Jin

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• H03M13/1575

  Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title