Method of forming internal spacer for nanowires

Patent metadata

Field	Value
Publication number	US-10153341-B2
Application number	US-201715822275-A
Country	US
Kind code	B2
Filing date	Nov 27, 2017
Priority date	Dec 9, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising horizontal nanowires, the method comprising:
providing a semiconductor structure comprising at least one fin, the at least one fin comprising a stack of layers of a sacrificial material alternated with layers of a nanowire material, the semiconductor structure comprising a dummy gate partly covering the stack of layers of the at least one fin;
at least partly removing the sacrificial material, in between the layers of the nanowire material, next to the dummy gate thereby forming a void;
providing spacer material within the void thereby forming an internal spacer;
removing the dummy gate; and
selectively removing the sacrificial material in a part of the at least one fin which was covered by the dummy gate, thereby releasing nanowires,
wherein the sacrificial material, in between the layers of the nanowire material, next to the dummy gate is removed and the internal spacer is provided before removing the dummy gate and the sacrificial material so as to release the nanowires,
wherein providing the spacer material comprises (i) a first step where a first material is filled bottom up and (ii) a second step comprising a continuous fill with a second material.

2. The method according to claim 1 , wherein the semiconductor structure further comprises a dummy gate spacer next to the dummy gate, and an inter-level dielectric (ILD) next to the dummy gate spacer such that the dummy gate spacer is in between the dummy gate and the ILD, the method further comprising:
before at least partly removing the sacrificial material next to the dummy gate, removing the dummy gate spacer thereby forming a trench,
wherein the at least partly removing the sacrificial material is started from an opening which is formed by the trench,
wherein providing the spacer material additionally comprises providing spacer material in the trench thereby forming the internal spacer next to the dummy gate.

3. The method according to claim 1 , further comprising:
depositing gate dielectric material around the nanowires; and
depositing gate material around the gate dielectric material thereby forming a gate.

4. The method according to claim 3 , the method further comprising:
forming a source at one side of the nanowire material next to the dummy gate or the gate; and
forming a drain at an opposite end of the nanowire material at an opposite side of the dummy gate or the gate.

5. The method according to claim 1 , wherein providing the spacer material comprises filling the spacer material from a bottom portion of the void toward a top portion of the void.

6. The method according to claim 1 , wherein providing the spacer material comprises refilling the void and/or a trench with at least one of: a liner, FCVD oxide or spin on material.

7. The method according to claim 1 , wherein the at least partly removing the sacrificial material is done by isotropic etching.

8. The method according to claim 1 , wherein providing the semiconductor structure comprises depositing a stack of layers on a substrate, the stack of layers comprising layers of sacrificial material alternated with layers of nanowire material and forming at least one fin in the stack of layers.

9. The method according to claim 8 , wherein the depositing the stack of layers on the substrate comprises depositing at least two layers of nanowire material.

10. The method according to claim 8 , wherein the depositing the stack of layers on the substrate comprises depositing at least three layers of nanowire material.

11. The method according to claim 8 , wherein the depositing the stack of layers on the substrate comprises depositing layers of nanowire material, wherein the layers of nanowire material comprise at least one of Silicon, SiGe, Ge, InGaAs, or III-V material.

12. The method according to claim 8 , wherein the depositing the stack of layers on the substrate comprises depositing Ge nanowire material layers and SiGe sacrificial material layers.

13. The method according to claim 8 , wherein the depositing the stack of layers on the substrate comprises depositing Si nanowire material layers and SiGe sacrificial material layers.

14. The method according to claim 1 , wherein providing the spacer material comprises depositing at least one of: silicon nitride, SiC:O, an FCVD oxide, or SiN.

15. A method of forming a semiconductor device, the method comprising:
providing a semiconductor structure comprising at least one fin, the at least one fin comprising a stack of layers of a sacrificial material alternated with layers of a nanowire material, the semiconductor structure comprising a dummy gate partly covering the stack of layers of the at least one fin;
at least partly removing the sacrificial material, in between the layers of the nanowire material, next to the dummy gate so as to form a void;
forming an internal spacer by providing spacer material within the void; and
after forming the internal spacer, (i) removing the dummy gate and (ii) selectively removing the sacrificial material in a part of the fin which was covered by the dummy gate, so as to release nanowires,
wherein forming the internal spacer comprises (i) a first step where a first material is filled from a bottom portion of the void toward a top portion of the void and (ii) a second step comprising a continuous fill with a second material.

16. The method according to claim 15 , further comprising:
depositing gate dielectric material around the nanowires; and
depositing gate material around the gate dielectric material thereby forming a gate.

17. The method according to claim 16 , further comprising:
forming a source at one side of the nanowire material next to the dummy gate or the gate; and
forming a drain at an opposite end of the nanowire material at an opposite side of the dummy gate or the gate.

18. The method according to claim 15 , wherein forming the internal spacer comprises filling the spacer material from a bottom portion of the void toward a top portion of the void.

Assignees

• Imec Vzw

Inventors

• Tao Zheng
• Chan Boon Teik
• Chew Soon Aik

Classifications

• H10P14/6342

  Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title