Compact and reliable changeable negative voltage transmission circuit

Patent metadata

Field	Value
Publication number	US-10153279-B2
Application number	US-201715431796-A
Country	US
Kind code	B2
Filing date	Feb 14, 2017
Priority date	Feb 15, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A compact and reliable changeable negative voltage transmission circuit is described. It is very useful for applications need passing changeable negative voltage to selected pins in certain mode. The changeable negative voltage is 0V when enable signal EN is low and −V 1 when enable signal EN is high. The circuit includes a control circuit and an output circuit. The control circuit includes a control high power source V DD and a control low power source V NEG . The control circuit generates control output signals CON and CON_B to the output circuit to output either 0V if IN is low or −V 1 if IN is high when EN is high. Only single type V T transistor is used in the transmission circuit without any reliability concern, no extra bias voltage is need, which reduces the area and keeps the manufacturing cost low.

First claim

The invention claimed is:

1. A circuit for passing a negative changeable voltage (V NEG ) comprising:
the negative voltage V NEG has a negative high state=−V 1 and a negative low state=10V;
a control circuit block disposed between control high and control low power sources, the control low power source is V NEG , wherein
the control circuit block is configured to receive
an enable signal EN having an enable active state and an enable inactive state, wherein V NEG is equal to −V 1 when EN is is active and V NEG =0V when EN is inactive, and
an input signal IN having an input active state and an
input inactive state, and

the control circuit block is configured to generate first and second output control signals CON and CON_B in response to IN; and

an output circuit block disposed between output high and output low power sources, wherein
the output circuit block is configured to receive the CON and CON_B signals from the control circuit block, and
the output circuit block is configured to generate an output signal OUT, wherein
OUT=0V when IN is inactive and EN is active,
OUT=−V 1 when IN is active and EN is active, and
OUT=0V when EN is inactive.

2. The circuit of claim 1 wherein:
the active EN=logic 1; and
the inactive EN=logic 0.

3. The circuit of claim 1 wherein −V 1 =−3V.

4. The circuit of claim 1 wherein:
CON and CON_B are complementary signals;
CON and CON_B have
a first control high state=V DD ,
a second control high state <V DD ,
a first control low state=0V, and
a second control low state=−V 1 ;

CON is either in the second control high state or the second control low state in response to IN when EN is in the enable high state;
CON_B is either in the second control low state or the second control high state in response to IN when EN is in the enable high state;
CON is either in the first control high state or the first control low state in response to IN when EN is in the enable low state; and
CON_B is either in the first control low state or the first control high state in response to IN when EN is in the enable low state.

5. The circuit of claim 4 wherein the control block comprises a reset circuit, the reset circuit is configured to generate a reset pulse ENR_P when EN switches from the inactive enable state to active enable state, wherein the pulse causes
CON to be go from the first control high/low state to the second control high/low state; and
CON_B to be go from the first control low/high state to the second control low/high state.

6. The circuit of claim 1 wherein the control block comprises a level shifter.

7. The circuit of claim 1 wherein the control block comprises:
an enable sub-block coupled in series to the control high power source, the enable sub-block is configured to receive the EN signal;
an input sub-block coupled in series to the enable sub-block, wherein the coupling between the enable and input sub-blocks forms a node NM, the input sub-block is configured to receive IN and a complementary input signal INB, wherein IN and INB are complementary signals;
a clamp sub-block in series to the input sub-block;
a pull-down sub-block coupled in series between the claim sub-block and the control low power source, the pull-down sub-block is configured to pull down CON or CON_B signal to V NEG , depending on IN;
first and second control outputs are configured to provide output control signals CON and CON_B signals, the first and second control output s are coupled between the clamp and pull-down sub-blocks, the clamp sub-block maintains NA and NB to be higher than V SS (0V), wherein maintaining NA and NB higher than V SS avoids reliability issues with transistors of the various sub-blocks, including the enable, input and reset sub-blocks; and
a reset sub-block, the reset sub-block have a first reset coupled between the enable and input sub-blocks and a second reset coupled to the clamp sub-block, the reset circuit is configured to reset the control block when EN goes from the enable low state to the enable high state, wherein the pulse causes
CON to be go from the first control high/low state to the second control high/low state; and
CON_B to be go from the first control low/high state to the second control low/high state.

8. The circuit of claim 7 wherein V NM <V DD .

9. The circuit of claim 7 wherein the sub-blocks which are coupled in series between the high and low control power sources and form first and second current paths between the high and low control power sources.

10. The circuit of claim 1 wherein the control block comprises:
a plurality of transistors coupled in series between high and low control power sources;
first and second current paths formed by the plurality of transistors coupled in series between the high and low control power sources;
wherein the plurality of transistors comprise p-type and n-type transistors;
wherein each transistor of the plurality of transistors comprises a gate between first and second S/D s and a body; and
wherein the transistors form sub-blocks of the control block which include
an enable sub-block,
an input sub-block,
a clamp sub-block,
a pull-down sub-block, and
a reset sub-block.

11. The circuit of claim 10 wherein:
the output block includes transistors; and
the transistors of the control block and the transistors of the output block are all the same gate threshold voltage (V T ) type transistors.

12. The circuit of claim 10 wherein:
the first current path between the high and low control power source comprises
an n-type transistor MN 5 having a first S/D terminal of MN 5 coupled to the control high power source,
a p-type transistor MP 1 having a first S/D terminal of MP 1 coupled to a second S/D terminal of MN 5 ,
a p-type transistor MP 3 having a first S/D terminal of MP 3 coupled to a second S/D terminal of MP 1 , wherein the first S/D terminal of MP 3 and the second S/D terminal of MP 1 from a node NA,
a n-type transistor MN 3 having a first S/D terminal of MN 3 coupled to a second S/D terminal of MP 3 , and
a n-type transistor MN 1 having a first S/D terminal of MN 1 coupled to a second S/D terminal of MN 3 and a second S/D terminal of MN 1 is coupled to the low control power source;

the second current path between the high and low control power source comprises
a p-type transistor MP 5 having a first S/D terminal of MP 5 coupled to the control high power source,
a p-type transistor MP 2 having a first S/D terminal of MP 2 coupled to a second S/D terminal of MP 5 ,
a p-type transistor MP 4 having a first S/D terminal of MP 4 coupled to a second S/D terminal of MP 2 , wherein the first S/D terminal of MP 4 and the second S/D terminal of MP 2 from a node NB,
a n-type transistor MN 4 having a first S/D terminal of MN 4 coupled to a second S/D terminal of MP 4 , and
a n-type transistor MN 2 having a first S/D terminal of MN 2 coupled to a second S/D terminal of MN 4 and a second S/D terminal of MN 2 is coupled to the low control power source; and

a n-type transistor MN 6 , wherein
a first S/D terminal of MN 6 is commonly coupled to the second S/D terminals of MN 5 and MP 5 and first S/D terminals of MP 1 and MP 2 to form node NM, and
a second S/D terminal of MN 6 is coupled to a gate terminal of MP 4 , the second S/D terminal is commonly coupled to a body terminal of MN 6 which is coupled to 0V.

13. The circuit of claim 12 wherein:
MN 5 and MP 5 forms the enable sub-block in which
a gate terminal of MN 5 is coupled to the control high power source,
a body terminal of MN 5 is coupled to 0V,
a gate of MP 5 is configure

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Xu Fei
• Nguyen Bai Yen
• Wang Jinling
• Lau Benjamin Shui Chor

Classifications

• H01L27/092 Primary

  Electricity · mapped topic

• H03K3/356182 Primary

  with additional means for controlling the main nodes · CPC title

• H01L27/0883

  Electricity · mapped topic

• H01L21/823493

  Electricity · mapped topic

• H01L27/11546

  Electricity · mapped topic