Semiconductor system and semiconductor package

Patent metadata

Field	Value
Publication number	US-9275755-B2
Application number	US-201314031867-A
Country	US
Kind code	B2
Filing date	Sep 19, 2013
Priority date	May 28, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A semiconductor system includes a plurality of memory chips. Each of the memory chips includes an oscillator suitable for generating a periodic wave in a self refresh mode, and a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based on a corresponding chip identification.

First claim

What is claimed is:

1. A semiconductor system comprising a plurality of memory chips, wherein each of the memory chips comprises:
an oscillator suitable for generating a periodic wave in a self refresh mode;
a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based on a corresponding chip identification; and
an arithmetic unit for receiving a preceding chip identification generated from an arithmetic unit of a preceding memory chip to generate the corresponding chip identification, wherein the corresponding chip identification is generated by adding a predetermined value to the received preceding chip identification.

2. The semiconductor system of claim 1 , wherein each of the memory chips performs a refresh operation whenever the corresponding refresh pulse is activated.

3. The semiconductor system of claim 1 , wherein each of the memory chips further comprises a refresh control unit suitable for controlling rows to be sequentially activated in the corresponding memory chip, whenever the corresponding refresh pulse is activated.

4. The semiconductor system of claim 1 , wherein the memory chips are stacked in one semiconductor package.

5. The semiconductor system of claim 4 , wherein an arithmetic unit provided in the most preceding memory chip receives an initial value.

6. A semiconductor system comprising a master chip and a plurality of slave chips,
wherein the master chip comprises an oscillator suitable for generating a periodic wave in a self refresh mode, and
each of the slave chips comprises a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based on a corresponding chip identification,
wherein each of the slave chips comprises an arithmetic unit for receiving a preceding chip identification generated from an arithmetic unit of a preceding chip to generate the corresponding chip identification, and
wherein the corresponding chip identification is generated by adding a predetermined value to the received preceding chip identification.

7. The semiconductor system of claim 6 , wherein the master chip performs a refresh operation whenever the periodic wave is activated, and each of the slave chips performs a refresh operation whenever the corresponding refresh pulse is activated.

8. The semiconductor system of claim 6 , wherein the master chip further comprises a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based on the corresponding chip identification, and
each of the master chip and the slave chips performs a refresh operation whenever the corresponding refresh pulse is activated.

9. The semiconductor system of claim 8 , wherein the master chip and the slave chips are stacked in one semiconductor chip.

10. The semiconductor system of claim 9 , wherein the slave chip comprises an arithmetic unit suitable for receiving an initial value.

11. A semiconductor system comprising a plurality of memory chips,
wherein each of the memory chips comprises:
a delay unit suitable for delaying an auto refresh command to generate a refresh pulse and for setting a delay value based on a corresponding chip identification; and
an arithmetic unit for receiving a preceding chip identification generated from an arithmetic unit of a preceding memory chip to generate the corresponding chip identification, wherein the corresponding chip identification is generated by adding a predetermined value to the received preceding chip identification.

12. The semiconductor system of claim 11 , wherein each of the memory chips performs a refresh operation whenever the refresh pulse is activated.

13. The semiconductor system of claim 11 , wherein each of the memory chips further comprises a refresh control unit suitable for controlling rows to be sequentially activated in the corresponding memory chip, whenever the corresponding refresh pulse is activated.

14. The semiconductor system of claim 11 , wherein the plurality of memory chips are stacked in one semiconductor package.

15. A semiconductor system comprising a plurality of memory chips suitable for performing respective refresh operations based on single refresh command,
wherein timing of the respective refresh operations is separated from each other by using chip identifications assigned to the respective memory chips, and
an arithmetic unit suitable for receiving a preceding chip identification generated from an arithmetic unit of a preceding memory chip to generate the corresponding chip identification, wherein the corresponding chip identification is generated by adding a predetermined value to the received preceding chip identification.

16. The semiconductor system of claim 15 , wherein the memory chips enter a self refresh mode based on a self refresh entry command, and exit from the self refresh mode based on a self refresh exit command.

17. The semiconductor system of claim 15 , wherein the memory chips perform the respective refresh operations based on an auto refresh command.

18. A semiconductor package comprising:
a master memory chip with command decoder suitable for generating an internal self refresh command; and
a plurality of slave memory chips sequentially stacked on the master memory chip, wherein each of the slave memory chips receives the internal self refresh command through an internal channel and generates a respective refresh pulse based on a corresponding chip identification,
wherein each of the slave memory chip comprises an arithmetic unit for receiving a preceding chip identification generated from an arithmetic unit of a preceding chip to generate the corresponding chip identification, and
wherein the corresponding chip identification is generated by adding a predetermined value to the received preceding chip identification.

19. The semiconductor package of claim 18 , wherein each of the respective refresh pulses is activated with a predetermined interval.

20. The semiconductor package of claim 18 , wherein each of slave memory chips comprises:
an oscillator suitable for generating a periodic wave with a predetermined frequency based on the internal self refresh command; and
a delay unit suitable for delaying the periodic wave to generate the respective refresh pulse, wherein the delay unit set a delay value based on the corresponding chip identification.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jung-Hyun

Classifications

• G11C29/028 Primary

  with adaption or trimming of parameters · CPC title

• G11C2211/4067

  Refresh in standby or low power modes · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title