Host bus access by add-on devices via a network interface controller

Patent metadata

Field	Value
Publication number	US-10152441-B2
Application number	US-201615154945-A
Country	US
Kind code	B2
Filing date	May 14, 2016
Priority date	May 18, 2015
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

Peripheral apparatus for use with a host computer includes an add-on device, which includes a first network port coupled to one end of a packet communication link and add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data. A network interface controller (NIC) includes a host bus interface, configured for connection to the host bus of the host computer and a second network port, coupled to the other end of the packet communication link. Packet processing logic in the NIC is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the resources of the host computer.

First claim

The invention claimed is:

1. Peripheral apparatus for use with a host computer that includes a host bus and host resources, including a host processor, connected to the host bus, the apparatus comprising:
a packet communication link having first and second ends;
an add-on device, which comprises:
a first network port coupled to the first end of the packet communication link; and
add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data; and

a network interface controller (NIC), which comprises:
a host bus interface, configured for connection to the host bus;
a second network port, coupled to the second end of the packet communication link; and
packet processing logic, which is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the host resources,

wherein the host resources comprise a system memory, and wherein the NIC comprises a direct memory access (DMA) engine, which is configured to write and read data to and from the system memory via the host bus, including the data in the packets transmitted from the add-on device over the packet communication link.

2. Peripheral apparatus for use with a host computer that includes a host bus and host resources, including a host processor, connected to the host bus, the apparatus comprising:
a packet communication link having first and second ends;
an add-on device, which comprises:
a first network port coupled to the first end of the packet communication link; and
add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data; and

a network interface controller (NIC), which comprises:
a host bus interface, configured for connection to the host bus;
a second network port, coupled to the second end of the packet communication link;
packet processing logic, which is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the host resources; and
a third network port, which is configured to convey communications between the host computer and a packet data network while the second network port communicates with the add-on device over the packet communication link.

3. Peripheral apparatus for use with a host computer that includes a host bus and host resources, including a host processor, connected to the host bus, the apparatus comprising:
a packet communication link having first and second ends;
an add-on device, which comprises:
a first network port coupled to the first end of the packet communication link; and
add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data; and

a network interface controller (NIC), which comprises:
a host bus interface, configured for connection to the host bus;
a second network port, coupled to the second end of the packet communication link; and
packet processing logic, which is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the host resources,

wherein the add-on device comprises a switch, which is coupled between the first network port and the add-on logic, and is configured to convey communications, transmitted and received via the second network port, between the host computer and a packet data network, while transferring the packets to and from the add-on logic.

4. Peripheral apparatus for use with a host computer that includes a host bus and host resources, including a host processor, connected to the host bus, the apparatus comprising:
a packet communication link having first and second ends;
an add-on device, which comprises:
a first network port coupled to the first end of the packet communication link; and
add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data;

a network interface controller (NIC), which comprises:
a host bus interface, configured for connection to the host bus;
a second network port, coupled to the second end of the packet communication link; and
packet processing logic, which is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the host resources; and

a switch, which comprises:
a third port, which is connected to the first end of the packet communication link;
a fourth port, which is connected to communicate with the first port of the add-on device; and
a fifth port, which is connected to communicate with another entity over a further packet communication link.

5. The apparatus according to claim 1 , wherein the first and second network ports are configured to transmit the packets over the packet communication link in accordance with an Ethernet protocol.

6. The apparatus according to claim 1 , wherein a range of addresses on the host bus is assigned to the host bus interface, and a sub-range within the assigned range is assigned to the add-on device, and wherein the packet processing logic is configured to translate the transactions on the host bus that are directed to the addresses in the sub-range into corresponding packets for transmission over the packet communication link to the add-on device.

7. The apparatus according to claim 1 , wherein the add-on logic and the packet processing logic are configured to transmit and receive the packets over the packet communication link in accordance with a remote direct memory access (RDMA) protocol, which specifies addresses in the system memory to and from which the data in the packets are to be written and read by the DMA engine.

8. Peripheral apparatus for use with a host computer that includes a host bus and host resources, including a host processor, connected to the host bus, the apparatus comprising:
a packet communication link having first and second ends;
an add-on device, which comprises:
a first network port coupled to the first end of the packet communication link; and
add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data; and

a network interface controller (NIC), which comprises:
a host bus interface, configured for connection to the host bus;
a second network port, coupled to the second end of the packet communication link; and
packet processing logic, which is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the host resources,

wherein the host resources comprise a system memory, and wherein the packet processing logic is configured to read and execute work items posted in work queues i

Assignees

• Mellanox Technologies Ltd
• Mellanox Technologies Ltd

Inventors

• Liss Liran
• Raindel Shachar
• Raikin Shlomo
• Menachem Adi
• Itkin Yuval

Classifications

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• H04L49/3009

  Header conversion, routing tables or routing tags · CPC title