Dynamic compiler parallelism techniques

Patent metadata

Field	Value
Publication number	US-10152312-B2
Application number	US-201514602258-A
Country	US
Kind code	B2
Filing date	Jan 21, 2015
Priority date	Jan 21, 2014
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

Compiler techniques for inline parallelism and re-targetable parallel runtime execution of logic iterators enables selection thereof from the source code or dynamically during the object code execution.

First claim

What is claimed is:

1. A computing device comprising:
a compiler to receive source code, including a logic iterator, and convert to a first portion of machine code for execution on a central processing unit (CPU) of the computing device, wherein an intermediate representation of the logic iterator generated by the compiler includes a specifier of a particular target and execution policy;
a runtime library including a plurality of runtime environment algorithms including implementations of target and execution policies selected from a group consisting of ahead-of-time (AOT) compilation for execution on the CPU, just-in-time (JIT) compilation for sequential execution on the CPU, JIT compilation for parallel execution on the CPU, JIT compilation for parallel execution on a graphics processing unit (GPU) of the computing device, and runtime selectable compilation and execution; and
a runtime environment that executes the first portion of machine code on the CPU, including dynamically compiling the intermediate representation of the logic iterator into a second portion of machine code and executing the second portion of machine code on a particular GPU instead of on the CPU when the specifier of the particular target and execution policy indicates:
JIT compilation for execution on the particular GPU, or
runtime selectable compilation and execution on the particular GPU.

2. The computing device of claim 1 , wherein the source code is selected from a group consisting of a function, a functor, function pointer and lambda.

3. The computing device of claim 1 , wherein one or more of the plurality of runtime environment algorithms are operable to control data transfer for execution of the logic iterator on the GPU.

4. The computing device of claim 1 , further comprising the compiler to embed the intermediate representation of the logic iterator into the compiled first portion of machine code when the specifier of the particular target and execution policy indicates JIT compilation for sequential execution on the CPU, JIT compilation for parallel execution on the CPU, JIT compilation for execution on a GPU, or runtime selectable compilation and execution.

5. The computing device of claim 4 , further comprising:
the compiler to convert during runtime the intermediate representation of the logic iterator into a second portion of machine code for execution on the GPU when the specifier of the particular target and execution policy indicates JIT compilation for parallel execution on the GPU; and
a runtime environment for executing the second portion of the machine code on the GPU, wherein the logic iteration is parallel executed across a plurality of processing pipelines of the GPU.

6. The computing device of claim 5 , wherein the second portion of machine code is compiled for compute unified device architecture (CUDA) execution.

7. The computing device of claim 4 , further comprising:
the compiler to convert during runtime the intermediate representation of the logic iterator into a second portion of machine code for execution on the CPU when the specifier of the particular target and execution policy indicates JIT compilation for sequential execution on the CPU or JIT compilation for parallel execution on the CPU; and
a runtime environment for executing the machine code on the CPU.

8. The computing device of claim 7 , further comprising the runtime environment for sequentially executing the machine code on the CPU, when the specifier of the particular target and execution policy indicates JIT compilation for sequential execution on the CPU.

9. The computing device of claim 7 , further comprising the runtime environment for parallel executing the machine code across a plurality of threads and/or cores on the CPU, when the specifier of the particular target and execution policy indicates JIT serial compilation for parallel execution on the CPU.

10. The computing device of claim 1 , wherein the logic iterator comprises a parallel for_each iterator over a vector of stock data.

11. A method comprising:
receiving, by a compiler, source code including a logic iterator with a specifier of a particular target and execution policy;
accessing, by the compiler, a runtime library including a plurality of runtime environment algorithms including implementations of a target and execution policies selected from a group consisting of ahead-of-time (AOT) compilation for execution on a central processing unit (CPU), just in time (JIT) compilation for sequential execution on the CPU, JIT compilation for parallel execution on the CPU, JIT compilation for parallel execution on a graphics processing unit (GPU), and runtime selectable compilation and execution;
compiling, by the compiler, the source code into an intermediate representation including the specifier of the particular target and execution policy;
compiling, by the compiler utilizing the runtime library, the intermediate representation into a first portion of machine code for a particular CPU, wherein the intermediate representation of the logic iterator is embedded in the first portion of machine code when the specifier of the particular target and execution policy indicates JIT compilation for execution on a particular GPU; and
executing, by a runtime environment, the first portion of machine code on the particular CPU, including:
dynamically compiling, by the compiler at runtime, the intermediate representation of the logic iterator into a second portion of machine code and executing the second portion of machine code on the particular GPU instead of on the particular CPU, when the specifier of the particular target and execution policy indicates runtime selectable compilation and JIT compilation for execution on the particular GPU during execution of the first portion of machine code on the particular CPU.

12. The method according to claim 11 , wherein executing, by the runtime environment, the first portion machine code on the particular CPU, further includes dynamically compiling the intermediate representation of the logic iterator into the second portion machine code and executing on the particular GPU instead of on the CPU, when the specifier of the particular target and execution policy indicates runtime selectable compilation and execution, and during executing the first portion of machine code on the particular CPU a variable for the runtime selectable compilation and execution indicates JIT compilation and execution on the GPU.

13. The method according to claim 11 , wherein the second portion of code is executed on the particular CPU when the first portion of machine code on the particular CPU includes a variable for the runtime selectable compilation and execution indicates execution on the CPU.

14. The method according to claim 12 , wherein executing, by the runtime environment, the first portion of machine code on the particular CPU, further includes compiling, by the compiler at runtime, the intermediate representation of the logic iterator into a second portion of machine code and sequential executing on the particular CPU when the specifier of the particular target and execution policy indicates JIT compilation for sequential execution on the CPU.

15. The method according to claim 12 , wherein executing, by the runtime environment, the first portion of machine code on the particular CPU, further includes compiling, by the compiler at runtime, the intermediate representation of the logic iterator to machine code and parallel executing on the particular CPU when the specifier of the particular target and execution policy indicates JIT compilation for parallel execution on

Assignees

• Grover Vinod
• Lutz Thibaut
• Nvidia Corp

Inventors

• Grover Vinod
• Lutz Thibaut

Classifications

• G06F8/47

  Retargetable compilers · CPC title

• G06F8/4443 Primary

  Inlining · CPC title

• G06F9/4552

  Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title