Intelligent GPU memory pre-fetching and GPU translation lookaside buffer management

Patent metadata

Field	Value
Publication number	US-9563571-B2
Application number	US-201414262500-A
Country	US
Kind code	B2
Filing date	Apr 25, 2014
Priority date	Apr 25, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device performs translation lookaside buffer coherency for a translation lookaside buffer of the graphics processing unit of the device. In this embodiment, the device receives a request to remove an entry of the translation lookaside buffer of the graphics processing unit, where the device includes a central processing unit and the graphics processing unit. In addition, the entry includes a translation of virtual memory address of a process to a physical memory address of system memory of a central processing unit and the graphics processing unit is executing a compute task of the process. The device locates the entry in the translation lookaside buffer and removes the entry.

First claim

What is claimed is:

1. A non-transitory machine-readable medium having executable instructions to cause one or more processing units to perform a method to process a graphics processing unit page fault, the method comprising:
detecting a page fault of a process associated with a first page that stores content of a memory object;
determining if the page fault is associated with a graphics processing unit operation; and
in response to determining that the page fault is associated with a graphics processing unit operation,
analyzing the memory object for domain information of the memory object,
identifying a second page that is stored in persistent storage using the domain information,
pre-fetching the second page associated with the memory object into physical memory, and
mapping the second page to virtual memory of the process.

2. The non-transitory machine-readable medium of claim 1 , wherein the graphics processing unit operation is selected from the group consisting of a read of a virtual memory address corresponding to a page that is not stored in physical memory and a write to a virtual memory address corresponding to a page that is not stored in physical memory.

3. The non-transitory machine-readable medium of claim 1 , wherein the domain information is structural information of the memory object.

4. The non-transitory machine-readable medium of claim 1 , wherein if the page fault is associated with a graphics processing unit operation, analyzing the memory object for historical use.

5. The non-transitory machine-readable medium of claim 1 , wherein the memory object is selected from the group consisting of an array, an image, and a texture.

6. The non-transitory machine-readable medium of claim 1 , wherein the pre-fetching comprises:
allocating memory for the second page in physical memory; and
loading the second page into physical memory.

7. The non-transitory machine-readable medium of claim 1 , wherein the mapping comprises:
adding a page table entry for the second page to a shared page table that maps a virtual address of the second page to a physical address of the second page.

8. The non-transitory machine-readable medium of claim 1 , further comprising:
analyzing a historical access information of the memory object, wherein the memory object spans a plurality of pages; and
identifying the second page that is stored in persistent storage using the domain information and the historical access information.

9. A method to process a graphics processing unit page fault, the method comprising:
detecting a page fault of a process associated with a first page that stores content of a memory object;
determining if the page fault is associated with a graphics processing unit operation; and
in response to determining that the page fault is associated with a graphics processing unit operation,
analyzing the memory object for domain information of the memory object,
identifying a second page that is stored in persistent storage using the domain information,
pre-fetching the second page associated with the memory object into physical memory, and
mapping the second page to virtual memory of the process.

10. The method of claim 9 , wherein the domain information is structural information of the memory object.

11. The method of claim 9 , wherein if the page fault is associated with a graphics processing unit operation, analyzing the memory object for historical use.

12. The method of claim 9 , wherein the pre-fetching comprises:
allocating memory for the second page in physical memory; and
loading the second page into physical memory.

13. The method of claim 9 , wherein the domain information is structural information of the memory object.

14. The method of claim 9 , wherein the memory object is selected from the group consisting of an array, an image, and a texture.

15. The method of claim 9 , further comprising:
analyzing a historical access information of the memory object, wherein the memory object spans a plurality of pages; and
identifying the second page that is stored in persistent storage using the domain information and the historical access information.

16. The device of claim 9 , wherein the process further causes the processor to analyze a historical access information of the memory object, wherein the memory object spans a plurality of pages and identify the second page that is stored in persistent storage using the domain information and the historical access information.

17. A device that tracks virtual memory access by a graphics processing unit of the device, the device comprising:
a processor;
a memory coupled to the processor though a bus; and

a process executed from the memory by the processor that causes the processor to detect a page fault of a process associated with a first page that stores content of a memory object,
determine if the page fault is associated with a graphics processing unit operation; and in response to determining that the page fault is associated with a graphics processing unit operation, analyze the memory object for domain information of the memory object, identify a second page that is stored in persistent storage using the domain information, pre-fetch the second page associated with the memory object into physical memory, and map the second page to virtual memory of the process.

18. The device of claim 17 , wherein the graphics processing unit operation is selected from the group consisting of a read of a virtual memory address corresponding to a page that is not stored in physical memory and a write to a virtual memory address corresponding to a page that is not stored in physical memory.

19. The device of claim 17 , wherein the domain information is structural information of the memory object.

20. The device of claim 17 , wherein if the page fault is associated with a graphics processing unit operation, analyzing the memory object for historical use.

21. The device of claim 17 , wherein the memory object is selected from the group consisting of an array, an image, and a texture.

22. The device of claim 17 , wherein the process further causes the processor to pre-fetch by allocating memory for the second page in physical memory and loading the second page into physical memory.

23. The device of claim 17 , wherein the process further causes the processor to map by adding a page table entry for the second page to a shared page table that maps a virtual address of the second page to a physical address of the second page.

Assignees

• Apple Inc

Inventors

• Kumar Derek R

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F2212/654

  Look-ahead translation · CPC title