Microelectromechanical system (MEMS) on application specific integrated circuit (ASIC)

Patent metadata

Field	Value
Publication number	US-10150668-B2
Application number	US-201715484765-A
Country	US
Kind code	B2
Filing date	Apr 11, 2017
Priority date	Jun 28, 2013
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A method comprising:
coupling a microelectromechanical system (MEMS) having an active side and an inactive side to one or more interconnects; and
coupling the one or more interconnects directly to an application-specific integrated circuit (ASIC) having an active side and an inactive side opposite the active side;
wherein the MEMS, the ASIC, and the one or more interconnects define a cavity between the MEMS, the ASIC, and the one or more interconnects such that a face of the MEMS is exposed within the cavity.

2. The method of claim 1 , wherein the MEMS is a first MEMS, the cavity is a first cavity, and the one or more interconnects are first one or more interconnects, and further comprising:
coupling a second MEMS to a second one or more interconnects; and
coupling the second one or more interconnects directly to the ASIC;
wherein the ASIC, the second MEMS, and the second one or more interconnects define a second cavity.

3. The method of claim 2 , wherein coupling the first interconnect to the ASIC comprises coupling the first interconnect to a redistribution layer (RDL) of the ASIC.

4. The method of claim 2 , further comprising covering at least a portion of one of the active or inactive side of the ASIC with a mold compound, wherein the first cavity is substantially free of the mold compound.

5. The method of claim 2 , further comprising:
forming a third cavity in the ASIC; and
coupling the first MEMS with the ASIC within the third cavity.

6. The method of claim 2 , further comprising coupling the first MEMS with the ASIC via a wirebond.

7. The method of claim 2 , further comprising coupling the ASIC with a circuit board through a package-level interconnect.

8. The method of claim 7 , further comprising coupling the package-level interconnect with the inactive side of the first MEMS; and
coupling the package-level interconnect with the ASIC through a through silicon via (TSV) from the inactive side of the MEMS to the active side of the MEMS, wherein the TSV is coupled with the ASIC.

9. The method of claim 2 , further comprising:
coupling the first MEMS to one of the active side or the inactive side of the ASIC through the first one or more interconnects; and
electrically coupling the first MEMS to the other one of the active side or the inactive side of the ASIC through one or more through silicon vias (TSVs) in the ASIC, wherein the one or more TSVs are configured to provide an electrical pathway from the one of the active side or the inactive side of the ASIC to the other one of the active side or the inactive side of the ASIC.

10. A method comprising:
coupling a microelectromechanical system (MEMS) having an active side and an inactive side to one or more interconnects;
coupling the one or more interconnects directly to an application-specific integrated circuit (ASIC) having an active side and an inactive side opposite the active side;
coupling a package-level interconnect with the inactive side of the MEMS; and
coupling the package-level interconnect with the ASIC through a through silicon via (TSV) from the inactive side of the MEMS to the active side of the MEMS, wherein the TSV is coupled with the ASIC;
wherein the MEMS, the ASIC, and the one or more interconnects define a cavity between the MEMS, the ASIC, and the one or more interconnects.

11. The method of claim 10 , wherein the MEMS is a first MEMS, the cavity is a first cavity, and the one or more interconnects are first one or more interconnects, and further comprising:
coupling a second MEMS to a second one or more interconnects; and
coupling the second one or more interconnects directly to the ASIC;
wherein the ASIC, the second MEMS, and the second one or more interconnects define a second cavity.

12. The method of claim 11 , wherein coupling the first interconnect to the ASIC comprises coupling the first interconnect to a redistribution layer (RDL) of the ASIC.

13. The method of claim 11 , further comprising covering at least a portion of one of the active or inactive side of the ASIC with a mold compound, wherein the first cavity is substantially free of the mold compound.

14. The method of claim 11 , further comprising:
forming a third cavity in the ASIC; and
coupling the first MEMS with the ASIC within the third cavity.

15. A method comprising:
coupling a microelectromechanical system (MEMS) having an active side and an inactive side to one or more interconnects; and
coupling the one or more interconnects directly to an application-specific integrated circuit (ASIC) having an active side and an inactive side opposite the active side;
coupling the MEMS to one of the active side or the inactive side of the ASIC through the one or more interconnects; and
electrically coupling the MEMS to the other one of the active side or the inactive side of the ASIC through one or more through silicon vias (TSVs) in the ASIC, wherein the one or more TSVs are configured to provide an electrical pathway from the one of the active side or the inactive side of the ASIC to the other one of the active side or the inactive side of the ASIC;
wherein the MEMS, the ASIC, and the one or more interconnects define a cavity between the MEMS, the ASIC, and the one or more interconnects.

16. The method of claim 15 , wherein the MEMS is a first MEMS, the cavity is a first cavity, and the one or more interconnects are first one or more interconnects, and further comprising:
coupling a second MEMS to a second one or more interconnects; and
coupling the second one or more interconnects directly to the ASIC;
wherein the ASIC, the second MEMS, and the second one or more interconnects define a second cavity.

17. The method of claim 16 , wherein coupling the first interconnect to the ASIC comprises coupling the first interconnect to a redistribution layer (RDL) of the ASIC.

18. The method of claim 16 , further comprising covering at least a portion of one of the active or inactive side of the ASIC with a mold compound, wherein the first cavity is substantially free of the mold compound.

19. The method of claim 16 , further comprising:
forming a third cavity in the ASIC; and
coupling the first MEMS with the ASIC within the third cavity.

20. The method of claim 16 , further comprising coupling the first MEMS with the ASIC via a wirebond.

Assignees

• Intel Ip Corp

Inventors

• Ofner Gerald
• Meyer Thorsten
• Mahnkopf Reinhard
• Geissler Christian
• Augustin Andreas

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• B81B2207/012

  the micromechanical device and the control or processing electronics being separate parts in the same package · CPC title

• B81B2201/0235

  Accelerometers · CPC title

• H01L2224/48091

  Electricity · mapped topic