Array substrate, display panel and display device
US-9780122-B2 · Oct 3, 2017 · US
Array substrate, display panel and display device
US10147745B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10147745-B2 |
| Application number | US-201715693017-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 31, 2017 |
| Priority date | Apr 1, 2015 |
| Publication date | Dec 4, 2018 |
| Grant date | Dec 4, 2018 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
An array substrate, a display panel and a display device are provided. The array substrate includes: a substrate. A signal transmission line, first and second insulator layers, a pixel electrode layer and a common electrode layer are disposed on the substrate; wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line; and wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer, and the signal transmission line is electrically connected with the common electrode layer. A parasitic capacitance between the signal transmission line and the common electrode layer is reduced in the array substrate.
First claim
Opening claim text (preview).
What is claimed is: 1. An array substrate, comprising: a substrate, wherein a signal transmission line, a first insulator layer, a second insulator layer, a pixel electrode layer and a common electrode layer are disposed on the substrate; a semiconductor layer disposed on the substrate; a fourth insulator layer disposed on the semiconductor layer; a gate layer disposed on the fourth insulator layer; a gate insulator layer disposed on the gate layer; a data line layer disposed on the gate insulator layer, wherein a first electrode, a second electrode and a data line are disposed on the data line layer; and a third insulator layer disposed on the data line layer, wherein the common electrode layer, the first insulator layer, the signal transmission line, the second insulator layer and the pixel electrode layer are successively disposed on the third insulator layer; wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, wherein the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line; wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer; and wherein the signal transmission line is electrically connected with the common electrode layer. 2. The array substrate according to claim 1 , wherein the pixel electrode layer is electrically connected with the first electrode disposed on the data line layer through a first via hole disposed in the second insulator layer, the first insulator layer and the third insulator layer, wherein a second via hole is disposed in the first insulator layer, and wherein the signal transmission line is electrically connected with the common electrode layer through the second via hole. 3. An array substrate, comprising: a substrate, wherein a signal transmission line, a first insulator layer, a second insulator layer, a pixel electrode layer and a common electrode layer are disposed on the substrate; a gate layer disposed on the substrate; a gate insulator layer disposed on the gate layer; a semiconductor layer disposed on the gate insulator layer; a data line layer disposed on the gate insulator layer, wherein a first electrode, a second electrode and a data line are disposed on the data line layer; and a third insulator layer disposed on the data line layer; wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, wherein the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line; wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer; wherein the signal transmission line is electrically connected with the common electrode layer; and wherein the pixel electrode layer, the first insulator layer, the signal transmission line, the second insulator layer and the common electrode layer are successively disposed on the third insulator layer. 4. The array substrate according to claim 3 , wherein, the pixel electrode layer is electrically connected with the first electrode disposed on the data line layer through a first via hole disposed in the third insulator layer, wherein a second via hole is disposed in the second insulator layer, and wherein the signal transmission line is electrically connected with the common electrode layer through the second via hole. 5. An array substrate, comprising: a substrate, wherein a signal transmission line, a first insulator layer, a second insulator layer, a pixel electrode layer and a common electrode layer are disposed on the substrate; a semiconductor layer disposed on the substrate; a fourth insulator layer disposed on the semiconductor layer; a gate layer disposed on the fourth insulator layer; a gate insulator layer disposed on the gate layer; a data line layer disposed on the gate insulator layer, wherein a first electrode, a second electrode and a data line are disposed on the data line layer; and a third insulator layer disposed on the data line layer; wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, wherein the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line; wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer; wherein the signal transmission line is electrically connected with the common electrode layer; and wherein the pixel electrode layer, the first insulator layer, the signal transmission line, the second insulator layer and the common electrode layer are successively disposed on the third insulator layer. 6. The array substrate according to claim 5 , wherein, the pixel electrode layer is electrically connected with the first electrode disposed on the data line layer through a first via hole disposed in the third insulator layer, wherein a second via hole is disposed in the second insulator layer, and wherein the signal transmission line is electrically connected with the common electrode layer through the second via hole.
Assignees
Inventors
Classifications
pixel · CPC title
poly-Si · CPC title
Input devices, e.g. touch panels · CPC title
Electricity · mapped topic
common or background · CPC title
Patent family
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US10147745B2 cover?
- An array substrate, a display panel and a display device are provided. The array substrate includes: a substrate. A signal transmission line, first and second insulator layers, a pixel electrode layer and a common electrode layer are disposed on the substrate; wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode…
- Who is the assignee on this patent?
- Shanghai Tianma Micro Elect Co, Tianma Micro Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H01L27/124. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 04 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).