Array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-9780122-B2
Application number	US-201514862537-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Apr 1, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

An array substrate, a display panel and a display device are provided. The array substrate includes: a substrate, wherein a signal transmission line, a first insulator layer, a second insulator layer, a pixel electrode layer and a common electrode layer are disposed on the substrate, wherein the first insulator layer is disposed between the signal transmission line and the common electrode layer, and the second insulator layer is disposed between the pixel electrode layer and the common electrode layer, and wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer, and the signal transmission line is electrically connected with the common electrode layer. A parasitic capacitance between the signal transmission line and the common electrode layer is reduced in the array substrate.

First claim

What is claimed is:

1. An array substrate, comprising: a substrate, wherein a signal transmission line, a first insulator layer, a second insulator layer, a pixel electrode layer and a common electrode layer are disposed on the substrate;
wherein the first insulator layer is disposed on the signal transmission line, the common electrode layer is disposed on the first insulator layer, the second insulator layer is disposed on the common electrode layer, and the pixel electrode layer is disposed on the second insulator layer; and
wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer, and the signal transmission line is electrically connected with the common electrode layer.

2. The array substrate according to claim 1 , wherein the first insulator layer comprises silicon oxide, fluorine-doped silicon oxide, or carbon-doped silicon oxide.

3. The array substrate according to claim 1 , wherein the second insulator layer comprises Si 3 N 4 , HfO 2 , ZrO 2 , Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZnO, CeO 2 , Y 2 O 3 , or ferroelectric material.

4. The array substrate according to claim 1 , further comprising:
a gate layer disposed on the substrate;
a gate insulator layer disposed on the gate layer;
a semiconductor layer disposed on the gate insulator layer;
a data line layer disposed on the gate insulator layer, wherein a first electrode, a second electrode and a data line are disposed on the data line layer; and
a third insulator layer disposed on the data line layer,
wherein the signal transmission line, the first insulator layer, the common electrode layer, the second insulator layer and the pixel electrode layer are successively disposed on the third insulator.

5. The array substrate according to claim 4 , wherein a first via hole is disposed in the first insulator layer, and the signal transmission line is electrically connected with the common electrode layer through the first via hole.

6. The array substrate according to claim 1 , wherein a slotted region is disposed in the common electrode layer, and the signal transmission line is disposed corresponding to the slotted region.

7. A display panel using an array substrate, the display panel comprising:
a substrate, wherein a signal transmission line, a first insulator layer, a second insulator layer, a pixel electrode layer and a common electrode layer are disposed on the substrate;
wherein the first insulator layer is disposed on the signal transmission line, the common electrode layer is disposed on the first insulator layer, the second insulator layer is disposed on the common electrode layer, and the pixel electrode layer is disposed on the second insulator layer; and
wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer, and the signal transmission line is electrically connected with the common electrode layer.

8. A display device, comprising: the display panel according to claim 7 .

Assignees

• Shanghai Tianma Microelectronics Co Ltd
• Tianma Microelectronics Co Ltd

Inventors

• Yuan Yong
• Yu Quanpeng
• Cui Meng
• Huang Zhongshou

Classifications

• H01L27/124 Primary

  Electricity · mapped topic

• H01L27/1248

  Electricity · mapped topic

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title