Isolated circuit formed during back end of line process

Patent metadata

Field	Value
Publication number	US-10147722-B2
Application number	US-201615235878-A
Country	US
Kind code	B2
Filing date	Aug 12, 2016
Priority date	Aug 12, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A semiconductor die is disclosed upon which is formed direct current (DC) isolated first and second circuits. The first circuit is configured for electrical connection to a first ground. The second circuit is configured for electrical connection to a second ground. The first and second grounds can be at different potentials. The first and second circuits were formed using front end of line (FEOL) and back end of line (BEOL) processes. The first circuit includes a plurality of first devices, such as transistors, which were formed during the FEOL process, and the second circuit includes only second devices, such as transistors, which were formed during the BEOL process.

First claim

What is claimed is:

1. An apparatus comprising:
a semiconductor die including a semiconductor wafer; and
direct current (DC) isolated first and second circuits commonly formed on the semiconductor die;
wherein the first circuit is configured for electrical connection to a first ground that is external to the semiconductor die;
wherein the second circuit is configured for electrical connection to a second ground that is external to the semiconductor die;
wherein the first circuit comprises a plurality of first devices that were formed during a front end of line (FEOL) portion of a process for manufacturing the semiconductor die, the plurality of first devices including at least one device formed in the semiconductor wafer, and;
wherein the second circuit comprises a plurality of second devices that were formed during a back end of line (BEOL) portion of the process of manufacturing the semiconductor die;
wherein the second circuit does not include any devices formed in the semiconductor wafer.

2. The apparatus of claim 1 wherein an electrical isolation layer is formed between the first and second circuits, and wherein the electrical isolation layer is formed during the BEOL process.

3. The apparatus of claim 2 wherein the plurality of second devices comprises a first thin film transistor (TFT).

4. The apparatus of claim 1 wherein the first circuit comprises a circuit for generating a control signal for controlling the second circuit.

5. The apparatus of claim 4 further comprising a galvanic isolation device that is external to the semiconductor die, wherein the galvanic isolation device is between and in data communication with the first and second circuits.

6. The apparatus of claim 4 further comprising a device that is external to the semiconductor die, wherein the device is configured to transmit alternating current (AC) components of the control signal, but not a direct current (DC) component of the control signal, from the first circuit to the second circuit.

7. The apparatus of claim 1 further comprising:
first and second transistors, which are external to the semiconductor die, coupled in series between a voltage input and the first ground;
wherein the second circuit is configured to generate first and second control signals for controlling the first and second transistors, respectively, in response to a control signal generated by the first circuit.

8. The apparatus of claim 1 wherein the first circuit comprises at least one TFT, which was formed during the BEOL portion of the process for manufacturing the semiconductor die.

9. An apparatus comprising:
direct current (DC) isolated first and second circuits formed on a semiconductor die;
wherein the first circuit is configured for electrical connection to a first ground that is external to the semiconductor die;
wherein the second circuit is configured for electrical connection to a second ground that is external to the semiconductor die;
wherein the first circuit comprises a plurality of first devices that were formed during a front end of line (FEOL) portion of a process for manufacturing the semiconductor die, and;
wherein the second circuit comprises a plurality of second devices that were formed during a back end of line (BEOL) portion of the process of manufacturing the semiconductor die;
wherein the second circuit does not include devices that were formed during the FEOL portion of the process for manufacturing the semiconductor die; and
a third circuit formed on the semiconductor die;
wherein the third circuit is DC isolated from the first and second circuits;
wherein the third circuit comprises a third conductor that is configured for electrical connection to a third ground that is external to the semiconductor die;
wherein the third circuit comprises a plurality of third devices that are formed during the BEOL process.

10. An apparatus comprising
electrically isolated first and second circuits both commonly formed on a semiconductor die;
wherein the first circuit comprises a first conductor that is configured for electrical connection to a first ground that is external to the semiconductor die;
wherein the second circuit comprises a second conductor that is configured for electrical connection to a second ground that is external to the semiconductor die;
wherein the first circuit comprises first transistors formed in a semiconductor substrate of the semiconductor die, and;
wherein the second circuit does not include any transistors that are formed in the semiconductor substrate.

11. The apparatus of claim 10 wherein the first transistors are formed during a front end of line (FEOL) process, and wherein second transistors of the second circuit are formed during a back end of line (BEOL) process.

12. The apparatus of claim 11 wherein an electrical isolation layer is formed between the first and second circuits, and wherein the electrical isolation layer is formed during the BEOL process.

13. The apparatus of claim 11 wherein the second transistors comprises a first thin film transistor (TFT).

14. The apparatus of claim 10 wherein the first circuit comprises a circuit for generating a control signal for controlling the second circuit.

15. The apparatus of claim 14 further comprising a device that is formed on another semiconductor die, wherein the device is configured to transmit alternating current (AC) components of the control signal, but not a direct current (DC) component of the control signal, from the first circuit to the second circuit.

16. The apparatus of claim 10 further comprising a galvanic isolation device that is not formed on the semiconductor die, wherein the first and second circuits are in data communication with each other via the galvanic isolation device.

17. The apparatus of claim 10 further comprising:
first and second power transistors, which are formed on second and third dies, respectively, coupled in series between a voltage input and the first ground;
wherein the second circuit is configured to generate first and second control signals for controlling the first and second power transistors, respectively, in response to a control signal generated by the first circuit.

18. The apparatus of claim 10 further comprising:
a third circuit formed on the semiconductor die;
wherein the third circuit is DC isolated from the first and second circuits;
wherein the third circuit is configured for electrical connection to a third ground that is external to the semiconductor die.

19. The apparatus of claim 18 wherein the third circuit comprises third transistors that are not formed in the semiconductor substrate.

Assignees

• Renesas Electronics America Inc

Inventors

• Yoshida Kenji
• Sato Tetsuo
• Maeta Shigeru
• Kimura Toshio

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title