Multi-die integrated circuit device with capacitive overvoltage protection

Patent metadata

Field	Value
Publication number	US-10147689-B2
Application number	US-201815907445-A
Country	US
Kind code	B2
Filing date	Feb 28, 2018
Priority date	Aug 24, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.

First claim

The invention claimed is:

1. A method comprising:
providing an electronic device having a package, two or more die, a first lead coupled to a first die of the two or more die, and a second lead coupled to a second die of the two or more die; and
providing a capacitive coupling between the first and second leads so that electrostatic discharge current can flow between the first die and the second die during handing of the electronic device;
wherein providing the capacitive coupling comprises providing the capacitive coupling between a ground node of the first die and a ground node of the second die.

2. The method of claim 1 wherein providing the capacitive coupling comprises providing a capacitor.

3. The method of claim 2 wherein providing the electronic device comprises providing a lead frame having a plurality of leads including the first lead and the second lead and at least one die attach pad.

4. The method of claim 3 wherein providing the capacitor comprises coupling the capacitor to the lead frame.

5. The method of claim 3 wherein providing the lead frame comprises providing two or more die attach pads and providing the capacitor comprises coupling the capacitor between at least two of the die attach pads.

6. The method of claim 1 wherein providing the capacitive coupling comprises providing dielectric material positioned between the first and second die.

7. The method of claim 6 wherein providing the dielectric material comprises providing an adhesive.

8. The method of claim 6 wherein providing the electronic device comprises providing the first and second die in a back-to-back configuration with the dielectric material sandwiched between the first and second die.

9. The method of claim 2 wherein providing the electronic device further comprises:
providing a plurality of die, each die having a respective plurality of contacts; and
providing a plurality of capacitors, each capacitor coupled between at least one contact of the plurality of contacts of one of the die and at least one contact of the plurality of contacts of another of the die.

Assignees

• Allegro Microsystems Llc

Inventors

• Lamar Washington
• Klebanov Maxim

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/00

  Package configurations · CPC title