Method for analyzing a logic circuit

Patent metadata

Field	Value
Publication number	US-10146937-B2
Application number	US-201615248370-A
Country	US
Kind code	B2
Filing date	Aug 26, 2016
Priority date	Aug 31, 2015
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A method for a logic circuit including a plurality of components and channels which are each assigned functional properties in a circuit model to simulate how the logic circuit functions, where the circuit model, in a section of the method, is expanded by mechanisms for security analysis, and where in a further section of the method, the following method steps are implemented via a simulation unit, i.e., check whether the security property of the respective component and/or the respective channel corresponds to the security requirement of the security-relevant data and generate a security risk report if it does not correspond thereto, apply a modeled attack to a component and/or to a channel, and determine a vulnerability of the security property of the respective component and/or of the respective channel to the applied attack, and if there is vulnerability of the security property, generate an attack report.

First claim

What is claimed is:

1. A method for analyzing a logic circuit comprising a plurality of components expanded by a respective simulation unit and channels expanded by a respective simulation unit for interchanging data between said plurality of components, wherein, for a simulation of a way in which the logic circuit functions, each component and each channel is assigned functional properties in a circuit model, which in a section of the method, is expanded by mechanisms for security analysis such that a respective component or a respective channel is assigned at least one defined security property and such that security-relevant data is linked to at least one defined security requirement and to a security status, and such that in a further section of the method the following method steps are performed via at least one of (i) a respective simulation unit of the respective component and (ii) a respective simulation unit of the respective channel:
checking to determine whether a security property of at least one of the respective component and the respective channel expanded by the respective simulation unit corresponds to a security requirement of the security-relevant data and generating a security risk report if the security property does not correspond the security requirement of the security-relevant data;
applying a modeled attack to at least one of the respective component and the respective channel expanded by the respective simulation unit; and
determining a vulnerability of the security property of at least one of the respective component and the respective channel expanded by the respective simulation unit to the applied modeled attack and generating an attack report to protect the logic circuit from attacks if the vulnerability of the security property of at least one of the respective component and the respective channel expanded by the respective simulation unit to the applied modeled attack exists.

2. The method as claimed in claim 1 , wherein event data is generated as the result of the applied attack.

3. The method as claimed in claim 1 , wherein event data is generated as the result of the applied attack.

4. The method as claimed in claim 1 , wherein probability data is generated to determine the vulnerability of the respective security property.

5. The method as claimed in claim 4 , wherein risk data for evaluating the respective security property is derived from the probability data.

6. The method as claimed in claim 1 , wherein an attack is selected from a previously created library.

7. The method as claimed in claim 1 , wherein each attack is assigned at least one of an attack potential, an attack type and an attack time trigger.

8. The method as claimed in claim 1 , wherein an attack graph with a number of graph nodes is modeled, each graph node corresponding to an attack that is applied to at least one of a specific component and a specific channel.

9. The method as claimed in claim 8 , wherein a plurality of attack graphs are linked to one another, such that one attack graph is executed as a function of a progress of the execution of another attack graph.

10. The method as claimed in claim 1 , wherein the circuit model of the logic circuit is formed as a high-level model.

11. The method as claimed in claim 10 , wherein high-level model is an electronic system-level model.

12. The method as claimed in claim 1 , wherein the logic circuit comprises an integrated circuit.

13. The method as claimed in claim 12 , wherein the integrated circuit is one of an Application-Specific Integrated Circuit or a system-on-chip.

14. The method as claimed in claim 1 , wherein the logic circuit comprises a Field Programmable Gate Array.

Assignees

• Siemens Ag

Inventors

• Fischer Bernhard
• Matschnig Martin
• Taucher Herbert

Classifications

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F21/577

  Assessing vulnerabilities and evaluating computer system security · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F21/552 Primary

  involving long-term monitoring or reporting · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title