Memory access control
US-2017038997-A1 · Feb 9, 2017 · US
US10146654B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10146654-B2 |
| Application number | US-201815897214-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 15, 2018 |
| Priority date | Nov 14, 2016 |
| Publication date | Dec 4, 2018 |
| Grant date | Dec 4, 2018 |
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Disclosed aspects relate to controlling an electronic circuit having multiple units with at least one signal input each. A set of signal resources is determined by tracing back a dependency tree for each unit signal input until an endpoint representing a signal resource is reached. For each signal resource in the set a resource manager may be provided in dependence of its signal type. That resource manager may be assigned a set of signal inputs comprising each signal input in the circuit which was traced back to its respective signal resource. The resource manager is configured for controlling the signal resource. A control device may be provided to receive technical implementation requirements for one or more of the resource managers, detect conflicting requirements received for the one or more resource managers, and enable or disable one or more of the resource managers in response to the detected conflicting requirements.
Opening claim text (preview).
What is claimed: 1. A method for controlling an electronic circuit containing multiple units with at least one respective signal input, comprising: determining a set of signal resources by tracing back a dependency tree for each unit signal input until an endpoint representing a signal resource is reached; providing a resource manager for each signal resource in the set in dependence of a signal type, wherein the resource manager is configured for controlling the signal resource; partitioning the electronic circuit into at least one power domain partition, at least one clock domain partition, and at least one reset domain partition, wherein each resource manager of the one or more resource managers is generated for a respective one of a clock domain, a power domain, and reset domain; determining dependencies of each resource manager of the generated resource manager from other resource managers regarding respective sets of input signals, wherein dependencies are determined in accordance with a promise theory using each dependency as a promise; responsive to determining dependences of each resource manager, providing a control device, wherein the control device comprises: a receiver to receive technical implementation requirements for one or more of the resource managers, wherein the received technical requirements comprise: first requirements of a first test of the electronic circuit and second requirements of a second test of the electronic circuit; a conflict detector to detect conflicting requirements received for the one or more resource managers; and an enabler to enable or disable one or more of the resource managers in response to the detected conflicting requirements, wherein enabling or disabling the one or more of the resource managers comprises: executing the first and second tests in a parallel fashion when one or more resource managers are enabled; executing the first and second tests concurrently when or more resource managers are enabled; executing the first and the second tests sequentially when one or more resource managers are enabled; executing the first and second tests in parallel when one or more resource managers are disabled; executing the first and second tests in concurrently when or more resource managers are disabled; and executing the first and the second tests sequentially when or more resource managers are disabled; assigning to the resource manager a set of signal inputs comprising each signal input in the circuit traced back to a respective signal resource; pausing an execution of one of the first and second tests while executing the other test when executing the first and the second tests in parallel; and responsive to solving the conflict, continuing the execution of the one of the first and second tests.
using a dedicated service processor for test · CPC title
Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title
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