Load replay precluding mechanism

Patent metadata

Field	Value
Publication number	US-10146539-B2
Application number	US-201514950365-A
Country	US
Kind code	B2
Filing date	Nov 24, 2015
Priority date	Dec 14, 2014
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an advanced programmable interrupt controller (APIC), configured to perform interrupt operations.

First claim

What is claimed is:

1. An apparatus for reducing replays in an out-of-order processor, the apparatus comprising:
a first reservation station, coupled to a hold bus, configured to dispatch a first load micro instruction, and configured to detect and indicate on the hold bus if said first load micro instruction is a specified load micro instruction directed to retrieve an operand from one of a plurality of prescribed resources other than on-core cache memory, wherein said plurality of prescribed resources are shared by a plurality of cores of the out-of-order processor;
replay reducer circuitry configured to evaluate an unmodified opcode portion of a load micro instruction that implicates a non-core resource, in order to detect said specified load micro instruction directed to non-core resources;
a second reservation station, coupled to said hold bus, configured to dispatch one or more younger micro instructions therein that depend on said first load micro instruction for execution after a first number of clock cycles following dispatch of said first load micro instruction, and if on said hold bus, in response to the detection by the replay reducer circuit, the first reservation station indicates that said first load micro instruction is said specified load micro instruction, said second reservation station is configured to stall dispatch of said one or more younger micro instructions until said first load micro instruction has retrieved said operand;
load execution logic, coupled to said first reservation station, configured to receive and execute said first load micro instruction, wherein said load execution logic is further configured to enter a power savings state if no micro instructions are received for execution, and wherein, if said first load micro instruction is not said specified load micro instruction, said load execution logic indicates on a miss bus that said first load micro instruction fails to successfully execute when more than said first number of clock cycles are required to retrieve said operand, thus initiating a replay of said one or more younger micro instructions, and wherein, if said first load micro instruction is said specified load micro instruction, said load execution logic does not indicate that said first load micro instruction fails to successfully execute when more than said first number of clock cycles are required to retrieve said operand, thus precluding a replay of said one or more younger micro instructions; and
said plurality of prescribed resources which are disposed outside of said plurality of cores, comprising:
an advanced programmable interrupt controller (APIC), configured to perform interrupt operations.

2. The apparatus as recited in claim 1 , wherein the out-of-order processor comprises a multi-core processor, and wherein each core within said multi-core processor comprises said first and second reservation stations.

3. The apparatus as recited in claim 2 , wherein said one of said plurality of prescribed resources comprises said APIC, and wherein said APIC unit is disposed on the same die as said each core, yet is disposed external to said each core.

4. The apparatus as recited in claim 2 , wherein said one of said plurality of prescribed resources is not disposed on the same die as said multi-core processor, and wherein said one of said plurality of prescribed resources is accessed via a bus unit disposed on the same die as said multi-core processor, yet disposed external to said each core.

5. An apparatus for reducing replays, the apparatus comprising:
a multi-core processor, comprising a plurality of cores, wherein each of said plurality of cores comprises:
a first reservation station, coupled to a hold bus, configured to dispatch a first load micro instruction, and configured to detect and indicate on the hold bus if said first load micro instruction is a specified load micro instruction directed to retrieve an operand from one of a plurality of prescribed resources other than on-core cache memory, wherein said plurality of prescribed resources are shared by said plurality of cores of the multi-core processor;
replay reducer circuitry configured to evaluate an unmodified opcode portion of a load micro instruction that implicates a non-core resource, in order to detect said specified load micro instruction directed to non-core resources;
a second reservation station, coupled to said hold bus, configured to dispatch one or more younger micro instructions therein that depend on said first load micro instruction for execution after a first number of clock cycles following dispatch of said first load micro instruction, and if on said hold bus, in response to the detection by the reply reducer circuit, the first reservation station indicates that said first load micro instruction is said specified load micro instruction, said second reservation station is configured to stall dispatch of said one or more younger micro instructions until said first load micro instruction has retrieved said operand;
load execution logic, coupled to said first reservation station, configured to receive and execute said first load micro instruction, wherein said load execution logic is further configured to enter a power savings state if no micro instructions are received for execution, and wherein, if said first load micro instruction is not said specified load micro instruction, said load execution logic indicates on a miss bus that said first load micro instruction fails to successfully execute when more than said first number of clock cycles are required to retrieve said operand, thus initiating a replay of said one or more younger micro instructions, and wherein, if said first load micro instruction is said specified load micro instruction, said load execution logic does not indicate that said first load micro instruction fails to successfully execute when more than said first number of clock cycles are required to retrieve said operand, thus precluding a replay of said one or more younger micro instructions; and
said plurality of prescribed resources which are disposed outside of said plurality of cores, comprising:
an advanced programmable interrupt controller (APIC), configured to perform interrupt operations.

6. The apparatus as recited in claim 5 , wherein said multi-core processor comprises an x86-compatible multi-core processor.

7. The apparatus as recited in claim 5 , wherein said one of said plurality of prescribed resources comprises said APIC, wherein said APIC unit is disposed on the same die as said multi-core processor, yet is disposed external to said each of said plurality of cores.

8. The apparatus as recited in claim 5 , wherein said one of said plurality of prescribed resources is not disposed on the same die as said multi-core processor, and wherein said one of said plurality of prescribed resources is accessed via a bus unit disposed on the same die as said multi-core processor, yet disposed external to said each core.

9. A method for reducing replays in an out-of-order processor, the method comprising:
disposing a plurality of prescribed resources comprising an advanced programmable interrupt controller (APIC) configured to interrupt operations, wherein the plurality of prescribed resources are disposed outside of a plurality of cores of the out-of-order processor and shared by the plurality of cores;
via a first reservation station, dispatching a first load micro instruction, and detecting and indicating on a hold bus if the first load micro instruction is a specified load micro instruction directed to retrieve an operand from one of a plurality of prescribed resources other than on-core cache memory; and
via a replay reducer circuit configured to evaluate an unmodified opcode portion of

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Col Gerard M
• Eddy Colin
• Henry G Glenn

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F9/3824

  Operand accessing · CPC title