Processor that performs approximate computing instructions

Patent metadata

Field	Value
Publication number	US-9389863-B2
Application number	US-201414522512-A
Country	US
Kind code	B2
Filing date	Oct 23, 2014
Priority date	Feb 10, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

A processor includes a decoder that decodes an instruction that instructs the processor to perform subsequent computations in an approximate manner and a functional unit that performs the subsequent computations in the approximate manner in response to the instruction. An instruction instructs the processor to clear an error amount associated with a value stored in a general purpose register of the processor. The error amount indicates an amount of error associated with a result of a computation performed by the processor in an approximate manner. The processor also clears the error amount in response to the instruction. Another instruction specifies a computation to be performed and includes a prefix that indicates the processor is to perform the computation in an approximate manner. The functional unit performs the computation specified by the instruction in the approximate manner specified by the prefix.

First claim

The invention claimed is:

1. A processor, comprising:
a decoder, configured to decode an instruction that instructs the processor to perform subsequent computations in an approximate manner;
architectural registers configured to hold operands;
error storage associated with each architectural register that is configured to indicate an amount of error in a result stored in the architectural register; and
a functional unit, configured to receive one or more operands from the architectural registers and error amounts from the associated error storages, perform a subsequent computation on the operands in the approximate manner in response to the instruction, accumulate the error amounts associated with the one or more operands prior to the approximate computation with an error amount introduced by performing the approximate computation, and store the result and the accumulated error amount in a destination architectural register and its associated error storage.

2. The processor of claim 1 , wherein the instruction comprises a prefix that instructs the processor to perform the computations in the approximate manner.

3. The processor of claim 2 , wherein the prefix specifies a degree of accuracy less than a full degree of accuracy with which the processor is to perform the computations.

4. The processor of claim 1 ,
wherein the decoder is further configured to decode a second instruction that instructs the processor to perform second subsequent computations with a full degree of accuracy; and
wherein the functional unit is configured to perform the second subsequent computations with the full degree of accuracy in response to the second instruction.

5. The processor of claim 4 , wherein the second instruction comprises a prefix that instructs the processor to perform the second subsequent computations with the full degree of accuracy.

6. The processor of claim 1 , further comprising:
an approximation control register, configured to hold information specifying an approximation policy for the processor, wherein the approximation policy includes a specification of a maximum tolerable accumulated error amount over a plurality of instruction executions;
wherein the processor is configured to generate an exception when the amount of error stored in the error storage exceeds the specified maximum tolerable accumulated error amount.

7. The processor of claim 6 , wherein the approximation policy further specifies an amount of approximating that the functional unit should employ in each approximated calculation, wherein the functional unit is configured to tailor its approximation on the basis of the approximation amount, so that subsequent calculations are constrained both by the approximation amount and the maximum tolerable accumulated error amount.

8. The processor of claim 6 , wherein the processor is configured to determine a current system configuration and set an approximation policy on the basis of the current system configuration.

9. The processor of claim 8 , wherein the current system configuration includes a monitor resolution, and the processor is configured to set an approximation policy that accepts a relatively greater amount of error in video-related computations with a low-resolution monitor than with a high-resolution monitor.

10. The processor of claim 8 , wherein the current system configuration includes speaker quality, and the processor is configured to set an approximation policy that accepts a relatively greater amount of error in audio-related computations with a relatively lower quality speaker than with a relatively higher-quality monitor.

11. The processor of claim 8 , wherein the processor is configured to detect changes in the current system configuration and modify the approximation policy.

12. The processor of claim 1 , wherein the functional unit is configured to perform transcendental functions on input operands to generate a result based on a polynomial, wherein the functional unit is configured to select a first polynomial if instructed to perform a full-accuracy computation and a relatively lower-order second polynomial if instructed to perform an approximate computation.

13. The processor of claim 1 , wherein the functional unit is a divider configured with dividing logic and iteration control logic, wherein:
the dividing logic is configured perform an iterative division computation on the input operands to generate an intermediate result and an indication of an accuracy of the intermediate result during each of a plurality of iterations, and to feed the intermediate result back as an input to the dividing logic; and
the iteration control logic is configured to stop the iterations once an accuracy has reached a level specified in an approximation policy.

14. A method performed by a processor, the method comprising:
decoding, by the processor, an instruction that instructs the processor to perform subsequent computations in an approximate manner;
storing operands in architectural registers of the processor;
providing one or more operands along with error amounts associated with each operand to a functional unit of the processor, wherein the error amounts are stored in error storage associated with each architectural register;
performing, by the functional unit, the subsequent computations in the approximate manner in response to said decoding the instructions; and
accumulating the error amounts associated with the one or more operands prior to the approximate computation with an error amount introduced by performing the approximate computation; and
storing the result and the accumulated error amount in a destination register and its associated error storage.

15. The method of claim 14 , wherein the instruction comprises a prefix that instructs the processor to perform the computations in the approximate manner.

16. The method of claim 15 , wherein the prefix specifies a degree of accuracy less than a full degree of accuracy with which the processor is to perform the computations.

17. The method of claim 14 , further comprising:
decoding, by the processor, a second instruction that instructs the processor to perform second subsequent computations with a full degree of accuracy; and
performing, by the processor, the second subsequent computations with the full degree of accuracy in response to said decoding the second instruction.

18. The method of claim 17 , wherein the second instruction comprises a prefix that instructs the processor to perform the second subsequent computations with the full degree of accuracy.

19. The method of claim 14 , further comprising:
storing information specifying an approximation policy for the processor in an approximation control register, wherein the approximation policy includes a specification of a maximum tolerable accumulated error amount over a plurality of instruction executions;
generating an exception when the amount of error stored in the error storage exceeds the specified maximum tolerable accumulated error amount.

20. The method of claim 19 , determining a current system configuration and setting an approximation policy on the basis of the current system configuration.

21. The method of claim 20 , wherein the current system configuration includes a monitor resolution, the method further comprising setting an approximation policy that accepts a relatively greater amount of error in video-related computations with a low-resolution monitor than with a high-resolution monitor.

22. The method of

Assignees

• Via Tech Inc
• Via Alliance Semiconductor Co Ltd

Inventors

• Henry G Glenn
• Parks Terry
• Hooker Rodney E

Classifications

• G06F9/30185 Primary

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title