Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes

US10141509B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10141509-B2
Application numberUS-201715473922-A
CountryUS
Kind codeB2
Filing dateMar 30, 2017
Priority dateMar 30, 2017
Publication dateNov 27, 2018
Grant dateNov 27, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: depositing a first electrode, a first metal cap, a first metal film, and a first hardmask (HM) on a silicon surface, wherein the deposited first metal film contains one or more crystal grains, wherein the one or more crystal grains in the first metal film contain a plurality of respective grain boundaries; increasing respective sizes of the plurality of respective grain boundaries in the one or more crystal grains in the first metal film by subtractive etching; forming a resistive random access memory (RRAM) cell, wherein the RRAM cell contains a critical dimension that is inversely proportional to a diameter of each respective crystal grains in the first metal film; depositing the RRAM cell over the deposited first electrode; depositing a second electrode, a second metal cap, a second metal film, and a second hardmask (HM) over the deposited RRAM cell, wherein the second metal film contains one or more crystal grains, wherein a diameter of each of the one or more crystal grains of the second film corresponds inversely to the critical dimension of the RRAM cell; and depositing a spacer over the second HM. 2. The method of claim 1 , wherein depositing the first electrode, the first metal cap, the first metal film, and the first HM, comprises: etching the deposited first HM; and etching the deposited first electrode. 3. The method of claim 2 , further comprising: etching the deposited first metal cap; and etching the deposited first metal film. 4. The method of claim 3 , further comprising: coating a trench with a first dielectric material; and implementing chemical mechanical planarization (CMP) on the first dielectric layer. 5. The method of claim 1 , wherein depositing the second electrode, the second metal cap, the second metal film, and the second HM, comprises: patterning the deposited second HM. 6. The method of claim 5 , further comprising: patterning the deposited second metal film; and patterning the deposited second metal cap. 7. The method of claim 1 , further comprising: providing a protective layer by etching the spacer, wherein the spacer has a thickness between 1 nm to 20 nm. 8. The method of claim 7 , further comprising: coating with a second dielectric material around the etched spacer; and implementing CMP on: the second dielectric material and the etched spacer. 9. The method of claim 1 , wherein the one or more crystal grains in the first metal film and the second metal film, comprises: performing a planarization process on a metal layer in the first electrode and on a metal layer in the second electrode, wherein the planarization process sets a thickness of the metal layer in the first electrode and a thickness of the metal layer in the second electrode equal to an average grain size of the one or more crystal grains in the first metal film and second metal film.

Assignees

Inventors

Classifications

  • H10B63/80Primary

    Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10141509B2 cover?
Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10B63/80. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 27 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).