Methods and processes for forming devices from correlated electron material (CEM)

Patent metadata

Field	Value
Publication number	US-10141504-B2
Application number	US-201715414520-A
Country	US
Kind code	B2
Filing date	Jan 24, 2017
Priority date	Jan 24, 2017
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters. In embodiments, CEM devices fabricated at a first stage of a wafer fabrication process, such as a front-end-of-line stage, may differ from CEM devices fabricated at a second stage of a wafer fabrication process, such as a middle-of-line stage or a back-end-of-line stage, for example.

First claim

What is claimed is:

1. A wafer, comprising:
one or more first CEM devices to operate at a first layer of the wafer; and
one or more second CEM devices to operate at a second layer positioned over the first layer of the wafer, wherein the one or more second CEM devices to operate at the second layer of the wafer comprises a through-substrate via, and wherein
the one or more first CEM devices to operate at the first layer exhibit a performance profile different from the performance profile exhibited by the one or more second CEM devices to operate at the second layer positioned over the first layer of the wafer.

2. The wafer of claim 1 , wherein the one or more first CEM devices to operate at the first layer of the wafer comprises a transistor, a logic device, a diode, an access device, a sensor or a radio, or a combination thereof.

3. The wafer of claim 2 , wherein the one or more first CEM devices to operate at the first layer of the wafer comprises the logic device and exhibits a leakage current of less than 100.0 nA/micron under an applied voltage of less than 1.2 volts.

4. The wafer of claim 2 , wherein the performance profile exhibited by the one or more first CEM devices comprises a current flow responsive to one or more applied voltages.

5. The wafer of claim 1 , wherein the through-substrate via exhibits a resistance of less than 1.6 microohm-cm in a low-resistance state.

6. The wafer of claim 1 , wherein the through-substrate via exhibits a resistance of greater than 16.0 microohm-cm in a high-resistance state.

7. The wafer of claim 1 , wherein the one or more first CEM devices to operate at the first layer of the wafer comprise at least one spacer to fill at least a portion of a trench separating the one or more CEM devices from a second device or structure.

8. The wafer of claim 1 , wherein the one or more first CEM devices to operate at first layer of the wafer comprises a sloped sidewall having an angle of between approximately 45.0° and 90.0° .

9. The wafer of claim 1 , wherein the one or more second CEM devices to operate at the second layer positioned over the first layer of the wafer comprises a routing layer or an optical interconnect, or one or more elements of an antenna.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Shifren Lucian
• Reid Kimberly Gay
• Yeric Greg Munson
• Rathor Manuj
• Rosendale Glen Arnold

Classifications

• H10W90/00

  Package configurations · CPC title

• H01L45/145

  Electricity · mapped topic

• H01L45/10

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• H01L45/065

  Electricity · mapped topic