Photodiode structures

Patent metadata

Field	Value
Publication number	US-10141472-B2
Application number	US-201715408004-A
Country	US
Kind code	B2
Filing date	Jan 17, 2017
Priority date	Sep 11, 2014
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

First claim

What is claimed:

1. A method, comprising:
forming a waveguide structure in a dielectric layer;
forming an amorphous Ge material over an upper surface of the waveguide structure in a back end of the line (BEOL) metal layer; and
crystallizing the amorphous Ge material into a crystalline Ge structure by an annealing process with a metal layer in contact with the Ge material,
wherein the forming of the Ge material adjacent to the waveguide structure in a back end of the line (BEOL) metal layer comprises:
depositing a barrier layer of nitride directly on the upper surface of the waveguide structure, followed by a patterning of the barrier layer;
depositing the amorphous Ge material directly on the barrier layer, followed by a patterning of the amorphous Ge material;
opening a via to expose portions of the amorphous Ge material;
depositing the metal layer on the amorphous Ge material through the opening of the via; and
crystallizing of the amorphous Ge material through the annealing process to form the crystalline Ge structure aligned with the via.

2. The method of claim 1 , wherein the annealing process is at about 350° C. to 420° C.

3. The method claim 2 , wherein the metal layer is a metal seed layer formed in direct contact with the Ge material within the via formed to expose a surface of the amorphous Ge material, the annealing process is performed after deposition of the metal seed layer is formed in direct contact with the Ge material, within the via of the dielectric layer.

4. The method of claim 1 , wherein the metal layer is a metal seed layer of Ni in contact with the Ge material.

5. The method of claim 1 , wherein the metal layer is a germanide or a eutectic.

6. The method of claim 1 , wherein any unreacted metal layer is removed after the annealing process.

7. The method of claim 1 , wherein the metal layer is a metal seed layer deposited in a via and on a surface of the Ge material.

8. The method of claim 1 , wherein the metal layer is a metal seed layer deposited in two vias in a dielectric material composing BEOL wiring layers, offset from a center of the Ge material.

9. The method of claim 1 , wherein the metal layer is a metal seed layer deposited in one of at least two vias.

10. The method of claim 1 , wherein the crystallizing of the amorphous Ge material comprises:
forming at least one via in a dielectric material to expose the amorphous Ge material;
forming a metal seed layer in the at least one via;
annealing the metal seed layer at a temperature of about 350° C. to 420° C. to form a capping layer on the amorphous Ge material and to laterally crystallize the amorphous Ge material; and
removing any unreacted metal seed layer.

11. The method claim 10 , further comprising filling the via with metal, in contact with the amorphous Ge material.

12. The method of claim 11 , further comprising removing the capping layer such that the metal in the via is in direct contact with the metal.

13. The method of claim 1 , wherein the crystallizing the amorphous Ge material into the crystalline Ge structure comprises:
depositing the metal layer as a metal seed layer directly on the amorphous Ge material which has been exposed by etching a trench and the via in the dielectric layer; and
laterally crystallizing the amorphous Ge material by the annealing process between 350° C. and 420° C.

14. The method of claim 13 , wherein the metal seed layer is formed on sidewalls of the trench and via that exposes a surface of the amorphous Ge material prior to the deposition of the metal seed layer.

15. The method of claim 14 , further comprising forming a boundary layer in the crystallized Ge material, which is positioned to a side of the waveguide structure.

Assignees

• IBM

Inventors

• Ellis-Monaghan John J
• Gambino Jeffrey P
• Jaffe Mark D
• Peterson Kirk D

Classifications

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• Y02E10/50

  Photovoltaic [PV] energy · CPC title

• G02B6/12

  of the integrated circuit kind (electric integrated circuits H10B, H10D84/00 - H10D89/00, H10F19/00, H10F39/00, H10H29/00, H10K19/00, H10K39/00, H10K59/00, H10N19/00, H10N39/00, H10N59/00, H10N69/00, H10N79/00, H10N89/00) · CPC title

• H01P1/172

  using a dielectric element · CPC title

• G02B6/12004

  Combinations of two or more optical elements · CPC title