Complementary tunneling field effect transistor and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-10141434-B2
Application number	US-201715587781-A
Country	US
Kind code	B2
Filing date	May 5, 2017
Priority date	Nov 7, 2014
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A complementary tunneling field effect transistor and a manufacturing method are disclosed, which includes: a first drain region and a first source region that are disposed on a substrate, where they include a first dopant; a first channel that is disposed on the first drain region and a second channel that is disposed on the first source region; a second source region that is disposed on the first channel and a second drain region that is disposed on the second channel, where they include a second dopant; a first epitaxial layer that is disposed on the first drain region and the second source region, and a second epitaxial layer that is disposed on the second drain region and the first source region; and a first gate stack layer that is disposed on the first epitaxial layer, and a second gate stack layer that is disposed on the second epitaxial layer.

First claim

What is claimed is:

1. A complementary tunneling field effect transistor, comprising:
a first drain region and a first source region disposed on a substrate, wherein the first drain region and the first source region comprise a first dopant;
a first channel disposed on the first drain region and a second channel disposed on the first source region;
a second source region disposed on the first channel and a second drain region disposed on the second channel, wherein the second source region and the second drain region comprise a second dopant;
a first epitaxial layer disposed on the first drain region and the second source region, and a second epitaxial layer disposed on the second drain region and the first source region, wherein the first epitaxial layer covers a side wall of the first channel and the second source region, and the second epitaxial layer covers a side wall of the second channel and the second drain region;
a first gate stack layer disposed on the first epitaxial layer, and a second gate stack layer disposed on the second epitaxial layer;
a first isolator disposed on the second source region and the first drain region, and a second isolator disposed on the first source region and the second drain region, wherein the first isolator is in contact with the first epitaxial layer and the first gate stack layer, and the second isolator is in contact with the second epitaxial layer and the second gate stack layer; and
wherein the first drain region, the first channel, the second source region, the first epitaxial layer, and the first gate stack layer form a first tunneling field effect transistor, and the second drain region, the second channel, the first source region, the second epitaxial layer, and the second gate stack layer form a second tunneling field effect transistor.

2. The complementary tunneling field effect transistor according to claim 1 , wherein:
the first dopant is a P-type dopant and the second dopant is an N-type dopant, or the first dopant is an N-type dopant and the second dopant is a P-type dopant;
an impurity concentration of the first dopant and the second dopant is within a range from about 10 19 per cubic centimeter to 10 21 per cubic centimeter;
the first channel and the second channel are lightly doped layers or first insulation layers; and
an impurity concentration in the lightly doped layers is less than or equal to 10 15 per cubic centimeter.

3. The complementary tunneling field effect transistor according to claim 1 , wherein:
the first gate stack layer comprises a first gate medium layer and a first gate conductive layer, and the second gate stack layer comprises a second gate medium layer and a second gate conductive layer; and
the complementary tunneling field effect transistor further comprises:
a second insulation layer disposed on the second source region, the first gate stack layer, the first drain region, the first source region, the second gate stack layer, and the second drain region,
a first drain disposed on the first drain region, a first source disposed on the second source region, and a first gate disposed on the first gate conductive layer, and
a second drain disposed on the second drain region, a second source disposed on the first source region, and a second gate disposed on the second gate conductive layer.

4. The complementary tunneling field effect transistor according to claim 1 , further comprising:
a shallow isolation groove disposed between the first drain region and the first source region.

5. The complementary tunneling field effect transistor according to claim 1 , wherein:
materials of the substrate, the first drain region, the first source region, the second drain region, the second source region, the first epitaxial layer, the second epitaxial layer, the first channel, and the second channel comprise at least one of silicon, germanium, germanium silicon, or three-five compounds;
materials of the first gate medium layer and the second gate medium layer comprise at least one of silicon dioxide, silicon nitride, or high dielectric materials; and
materials of the first gate conductive layer and the second gate conductive layer comprise at least one of polycrystalline silicon, titanium nitride, or metal materials.

6. A complementary tunneling field effect transistor manufacturing method, comprising:
successively depositing a first doped layer, a channel layer, and a second doped layer on a substrate, wherein the first doped layer comprises a first dopant, and the second doped layer comprises a second dopant;
etching the second doped layer, the channel layer, and the first doped layer to form a second source region, a second drain region, a first channel, a second channel, a first drain region, and a first source region, wherein the first channel is located on the first drain region, the second source region is located on the first channel, the second channel is located on the first source region, and the second drain region is located on the second channel;
successively depositing an epitaxial layer and a gate stack layer on the second source region, the first drain region, the first source region, and the second drain region;
etching the gate stack layer and the epitaxial layer to successively form a first gate stack layer, a second gate stack layer, a first epitaxial layer, and a second epitaxial layer, wherein the first gate stack layer is located above the first epitaxial layer, the second gate stack layer is located above the second epitaxial layer, the first epitaxial layer covers a side wall of the first channel and the second source region, and the second epitaxial layer covers a side wall of the second channel and the second drain region;
disposing a first isolator on the second source region and the first drain region, and disposing, a second isolator on the first source region and the second drain region, wherein the first isolator is in contact with the first epitaxial layer and the first gate stack laver, and the second isolator is in contact with the second epitaxial layer and the second gate stack layer; and
wherein the first drain region, the first channel, the second source region, the first epitaxial layer, and the first gate stack layer form a first tunneling field effect transistor, and the second drain region, the second channel, the first source region, the second epitaxial layer, and the second gate stack layer form a second tunneling field effect transistor.

7. The manufacturing method according to claim 6 , wherein:
the first dopant is a P-type dopant and the second dopant is an N-type dopant, or the first dopant is an N-type dopant and the second dopant is a P-type dopant;
an impurity concentration of the first dopant and the second dopant is within a range from about 10 19 per cubic centimeter to 10 21 per cubic centimeter;
the first channel and the second channel are lightly doped layers or first insulation layers; and
an impurity concentration in the lightly doped layers is less than or equal to 10 15 per cubic centimeter.

8. The manufacturing method according to claim 6 , wherein:
the first gate stack layer comprises a first gate medium layer and a first gate conductive layer, and the second gate stack layer comprises a second gate medium layer and a second gate conductive layer;
after etching the gate stack layer and the epitaxial layer to successively form the first gate stack layer, the second gate stack layer, the first epitaxial layer, and the second epitaxial layer, the manufacturing method further comprises:
disposing a second insulation layer on the second source region, the first gate stack layer, the first drain region, the first source region, the second gate stack layer, and the second drain region; and

Assignees

• Huawei Tech Co Ltd

Inventors

• Yang Xichao
• Zhao Jing
• Zhang Chen-Xiong

Classifications

• H01L29/42392

  Electricity · mapped topic

• H01L21/823828

  Electricity · mapped topic

• H01L29/78651

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic