Semiconductor packages having through electrodes and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9287140-B2
Application number	US-201414264123-A
Country	US
Kind code	B2
Filing date	Apr 29, 2014
Priority date	Jun 27, 2013
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.

First claim

What is claimed is:

1. A method of forming a semiconductor package, the method comprising:
providing a first chip and a second chip, the providing comprising:
providing a first active layer on a front surface of a first substrate of the first chip; and
providing a second active layer on a front surface of a second substrate of the second chip;

stacking the first chip and the second chip so that the first active layer of the first chip faces the second active layer of the second chip;
forming a mold layer on the first chip and on the front surface of the second substrate of the second chip to provide rigidity to the semiconductor package, the mold layer including a polymer material;
thinning a back surface opposite to the front surface of the second substrate
forming back-side electrodes on the thinned back surface of the second substrate, the back-side electrodes being electrically connected to through electrodes of the second substrate; and
thinning a back surface of the first chip of the first substrate in the semiconductor package after the thinning the back surface of the second substrate of the semiconductor package.

2. The method of claim 1 , wherein the thinning the back surface of the second substrate comprises thinning the back surface of the second substrate using a mechanical process.

3. The method of claim 2 , wherein the thinning the back surface of the second substrate exposes the through electrodes of the second substrate, the through electrodes of the second substrate being electrically connected to the second active layer.

4. The method of claim 1 further comprising forming the through electrodes of the second substrate in the thinned second substrate before forming the back-side electrodes.

5. The method of claim 1 further comprising providing first connection electrodes between the first chip and the second chip to electrically connect the first active layer and the second active layer.

6. The method of claim 1 , wherein the providing the first and the second chips does not include bonding a carrier to any one of the first and the second chips and further does not include debonding the carrier from any one of the first and the second chips.

7. The method of claim 1 , wherein the first active layer comprises a first transistor and the second active layer comprises a second transistor.

8. The method of claim 1 , wherein a coefficient of thermal expansion (CTE) of the substrate of the second chip and a CTE of the mold layer are within an order of magnitude.

9. The method of claim 1 , wherein a ratio of a coefficient of thermal expansion (CTE) of the substrate of the second chip and a CTE of the mold layer is in a range from 1 to 3.

10. The method of claim 1 further comprising forming first back-side electrodes on the thinned back surface of the first substrate, the first back-side electrodes being electrically connected to a plurality of through electrodes of the first substrate, the plurality of through electrodes of the first substrate being electrically connected to the first active layer.

11. The method of claim 10 wherein the thinning the back surface of the first chip of the first substrate in the semiconductor package exposes the plurality of through electrodes of the first substrate.

12. A method of forming a plurality of semiconductor packages, the method comprising:
forming a first semiconductor package, the forming the first semiconductor comprising:
providing a first chip and a second chip, the providing the first and the second chips comprising:
providing a first active layer on a front surface of a first substrate of the first chip; and
providing a second active layer on a front surface of a second substrate of the second chip;

stacking the first chip and second chip so that the first active layer of the first chip faces the second active layer of the second chip;
forming a first mold layer on the first chip and on the front surface of the second substrate of the second chip to provide rigidity to the first semiconductor package, the first mold layer including a first polymer material;
thinning a back surface opposite to the front surface of the second substrate; and
forming back-side electrodes on the thinned back surface of the second substrate, the back-side electrodes being electrically connected to through electrodes of the second substrate;

forming a second semiconductor package, the forming the second semiconductor package comprising:
providing a third chip and a fourth chip, the providing the third and the fourth chips comprising:
providing a third active layer on a front surface of a third substrate of the third chip; and
providing a fourth active layer on a front surface of a fourth substrate of the fourth chip;

stacking the third chip and the fourth chip so that the third active layer of the third chip faces the fourth active layer of the fourth chip;
forming a second mold layer on the third chip and on the front surface of the fourth substrate of the fourth chip to provide rigidity to the second semiconductor package, the second mold layer including a second polymer material;
thinning a back surface opposite to the front surface of the fourth substrate; and
forming back-side electrodes on the third back surface of the fourth substrate, the back-side electrodes being electrically connected to through electrodes of the fourth substrate;

stacking the second semiconductor package on the first semiconductor package.

13. The method of claim 12 further comprising thinning a back surface of the first chip of the first substrate in the first semiconductor package after the thinning the back surface of the second substrate of the first semiconductor package.

14. The method of claim 13 further comprising forming first back-side electrodes on the thinned back surface of the first substrate, the first back-side electrodes being electrically connected to a plurality of through electrodes of the first substrate, the plurality of through electrodes of the first substrate being electrically connected to the first active layer.

15. The method of claim 14 wherein the thinning the back surface of the first chip of the first substrate in the first semiconductor package exposes the plurality of through electrodes of the first substrate.

16. The method of claim 14 further comprising forming the plurality of through electrodes in the thinned back surface of the first substrate before forming the first back-side electrodes.

17. The method of claim 11 further comprising forming the plurality of through electrodes in the thinned back surface of the first substrate before forming the first back-side electrodes.

18. The method of claim 12 , wherein the stacking the second semiconductor package comprises inverting the first semiconductor package so that the thinned back surface of the second chip faces upward.

19. The method of claim 18 , wherein the stacking the second semiconductor package further comprises stacking the second semiconductor package on the inverted first semiconductor package so that a back surface of the second semiconductor package faces the thinned back surface of the second chip of the first semiconductor package.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Hyunsoo
• Kim Jongyeon
• Lee In-Young
• Cho Tae-Je

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title