Method of fabricating semiconductor package structure

Patent metadata

Field	Value
Publication number	US-10141266-B2
Application number	US-201715621337-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Sep 17, 2014
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

First claim

What is claimed is:

1. A method of fabricating a semiconductor package structure, comprising:
providing a release member that has opposing top and bottom surfaces;
forming a plurality of first conductive pads and a plurality of second conductive pads on the top surface of the release member;
disposing a semiconductor component on the first conductive pads and electrically connecting the semiconductor component to the first conductive pads, forming a plurality of conductive elements on the second conductive pads, each of the conductive elements having opposing first and second ends, and forming on the top surface of the release member a package body having opposing first and second surfaces and encapsulating the semiconductor component and the conductive elements, with the first and second conductive pads exposed from the first surface of the package body, and the second ends of the conductive elements exposed from the second surface of the package body; and
after forming the conductive elements on the second conductive pads, removing the release member.

2. The method of claim 1 , wherein the conductive elements are solder balls or metal pillars.

3. The method of claim 1 , further comprising, after the package body is formed, forming on the second surface of the package body an insulating layer having a plurality of first openings, from which the second ends of the conductive elements are exposed.

4. The method of claim 1 , further comprising, after the package body is formed, forming solder pads on the second ends of the conductive elements.

5. The method of claim 1 , further comprising, after the release member is removed, disposing a stack member on the first surface of the package body, and electrically connecting the package member to the first conductive pads and the second conductive pads.

6. A method of fabricating a semiconductor package structure, comprising:
providing a release member having opposing top and bottom surfaces;
forming a patterned first dielectric layer, from which a portion of the top surface of the release member is exposed;
forming a plurality of first conductive pads and a plurality of second conductive pads on the exposed portion of the top surface of the release member;
disposing a semiconductor component on the first conductive pads and electrically connecting the semiconductor component to the first conductive pads, forming a plurality of conductive elements on the second conductive pads, each of the conductive elements having opposing first and second ends, and forming on the first dielectric layer a second dielectric layer, in which the conductive elements and the semiconductor component are embedded, the first and second dielectric layers forming a package body that has a first surface coupled to the first dielectric layer and a second surface coupled to the second dielectric layer; and
after forming the conductive elements on the second conductive pads, removing the release member.

7. The method of claim 6 , wherein the conductive elements and the second dielectric layer are formed by:
forming the second dielectric layer on the first dielectric layer;
forming a plurality of through holes penetrating the second dielectric layer, with the second conductive pads being exposed therefrom; and
forming the conductive elements in the through holes.

8. The method of claim 7 , wherein the through holes are formed by laser drilling, machine drilling, or lithography technique.

9. The method of claim 6 , wherein the conductive elements and the second dielectric layer are formed by:
forming the conductive elements on the second conductive pads; and
forming on the first dielectric layer the second dielectric layer that encapsulates the conductive elements.

10. The method of claim 9 , further comprising, after the second dielectric layer is formed, removing a portion in thickness of the second dielectric layer, with the second ends of the conductive elements being exposed from the second surface of the package body.

11. The method of claim 6 , wherein the conductive elements are solder balls or metal pillars.

12. The method of claim 6 , further comprising, after the package body is formed, forming on the second surface of the package body an insulating layer having a plurality of first openings, from which the second ends of the conductive elements are exposed.

13. The method of claim 6 , further comprising, after the package body is formed, forming solder pads on the second ends of the conductive elements.

14. The method of claim 13 , wherein each of the solder pads comprises a conductive layer formed on the second end of a corresponding one of the conductive elements and a metal layer formed on the conductive layer.

15. The method of claim 13 , further comprising, after the solder pads are formed, forming a surface finish layer on exposed surfaces of the solder pads, the first conductive pads, and the second conductive pads.

16. The method of claim 6 , further comprising, after the release member is removed, disposing a stack member on the first surface of the package body, and electrically connecting the package member to the first conductive pads and the second conductive pads.

17. The method of claim 16 , wherein the stack member is disposed by:
disposing an electronic component on the first surface of the package body, and electrically connecting the electronic component to the first conductive pads and the second conductive pads; and
forming on the first surface of the package body an encapsulant, in which the electronic component is embedded.

18. The method of claim 16 , wherein the electronic component is a substrate, a semiconductor chip, an interposer, or a packaged or unpackaged semiconductor component.

19. The method of claim 6 , wherein the semiconductor component is an active component or a passive component.

20. The method of claim 6 , wherein the package body is made of a molding compound, a prepreg, or a photosensitive dielectric material.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Pai Yu-Cheng
• Hsiao Wei-Chung
• Chiu Shih-Chao
• Lin Chun-Hsien
• Sun Ming-Chen
• Shen Tzu-Chieh
• Chen Chia-Cheng

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title