Electronic package and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-10141233-B2
Application number	US-201615008097-A
Country	US
Kind code	B2
Filing date	Jan 27, 2016
Priority date	Jul 3, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.

First claim

What is claimed is:

1. An electronic package, comprising:
a first circuit structure having a first surface and a second surface opposite to the first surface, wherein the first circuit structure has at least a first redistribution layer;
a plurality of first electronic elements disposed on and directly attached to the first surface of the first circuit structure;
at least a first conductive element disposed on the first surface of the first circuit structure;
a first encapsulant formed on the first surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant, wherein the first encapsulant is in direct contact with the first circuit structure and the first electronic elements;
a first metal layer formed on the first encapsulant, wherein the first metal layer is a circuit layer and in direct contact with the first conductive element and the first encapsulant;
a second circuit structure formed on and being in direct contact with the second surface of the first circuit structure, wherein the second circuit structure has at least a second redistribution layer;
a plurality of second electronic elements bonded to the second circuit structure, wherein each of the second electronic elements is an active element, a passive element, or a combination thereof; and
a second encapsulant formed on the second circuit structure and encapsulating the second electronic elements, wherein the second encapsulant is in direct contact with the second circuit structure and the second electronic elements.

2. The electronic package of claim 1 , further comprising:
at least a second conductive element disposed on the second circuit structure; and
the second encapsulant encapsulating the second conductive element, with a portion of the second conductive element exposed from the second encapsulant.

3. The electronic package of claim 2 , further comprising a second metal layer formed on the second encapsulant.

4. The electronic package of claim 3 , wherein the second metal layer is in contact with the second conductive element.

5. The electronic package of claim 2 , further comprising a conductor wall formed on at least one of the second circuit structure and the first surface of the first circuit structure.

6. The electronic package of claim 5 , wherein the conductor wall formed on the second circuit structure is encapsulated by the second encapsulant, with a portion of the conductor wall on the second circuit structure exposed from the second encapsulant.

7. The electronic package of claim 5 , wherein the conductor wall formed on the first surface of the first circuit structure is encapsulated by the first encapsulant, with a portion of the conductor wall on the first surface of the first circuit structure exposed from the first encapsulant.

8. The electronic package of claim 2 , wherein a portion of the second circuit structure is exposed from the second encapsulant.

9. The electronic package of claim 1 , wherein a portion of the first circuit structure is exposed from the first encapsulant.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Lu-Yi
• Lu Chang-Lun

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title