Digitally calibrated successive approximation register analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10135455-B2
Application number	US-201715799812-A
Country	US
Kind code	B2
Filing date	Oct 31, 2017
Priority date	Nov 4, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator V d having a first input, a second input, and an output; a first plurality of capacitors C p [0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C n [0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator V d and the digital output port.

First claim

What is claimed is:

1. A system, comprising:
an analog input port;
a digital output port; and
a successive approximation register (SAR) analog-to-digital converter (ADC), the SAR ADC including:
a voltage comparator V d having a first input, a second input, and an output;
a first plurality of capacitors C p [0:n] that are coupled with the analog input port and each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with a common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a first input voltage V inp , a reference voltage V ref , the common mode voltage V cm , and ground, wherein the common mode voltage V cm is equal to one-half of the reference voltage V ref , and wherein the first plurality of capacitors C p [0:n] includes 8 capacitors C p [0:7];
a second plurality of capacitors C n [0:n] that are coupled with the analog input port and each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with the common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a second input voltage V inn , the reference voltage V ref , the common mode voltage V cm , and ground, wherein the second plurality of capacitors C n [0:n] includes 8 capacitors C n [0:7], wherein the first and second pluralities of capacitors together represent two 4-bit sections C[0:7], and wherein the two 4-bit sections include two most significant bits (MSBs) C[3] and C[7], each MSB having three corresponding least significant bits (LSBs) C[2:0] and C[6:4], respectively; and
a SAR controller coupled between the output of the voltage comparator V d and the digital output port, wherein the SAR controller is configured to implement a collapsible SAR algorithm that uses balanced ternary values (−1,0,+1) for each bit to encode an analog input.

2. The system of claim 1 , wherein a bit weight of each of the most significant bits (MSBs) C[3] and C[7] is equal to a sum of bit weights of the corresponding least significant bits (LSBs) C[2]+C[1]+C[0] and C[6]+C[5]+C[4], respectively.

3. The system of claim 2 , wherein the SAR controller is configured to implement a collapsible SAR algorithm that performs a comparison of the conversion residue to the mid-code of the remaining least significant bits (LSBs).

4. The system of claim 3 , wherein the collapsible SAR algorithm determines the most significant bit (MSB) value of the remaining least significant bits (LSBs) based on the polarity of the comparison.

5. The system of claim 1 , wherein the first and second pluralities of capacitors together represent 20 bits C[0:19] that include three collapsible 4-bit sections C[8:11], C[12:15], and C[16:19] that are implemented by way of a C-2C network.

6. The system of claim 5 , further comprising a bridge capacitor electrically coupled between two of the three collapsible 4-bit sections C[8:11] and C[12:15].

7. The system of claim 1 , wherein the first and second pluralities of capacitors together represent 20 bits C[0:19] that include three collapsible 4-bit sections C[8:11], C[12:15], and C[16:19], and wherein the unit capacitances of the three collapsible 4-bit sections C[8:11], C[12:15], and C[16:19] are different from each other.

8. The system of claim 1 , wherein each bottom plate of the first plurality of capacitors is electrically coupled with the first input voltage V inp , each bottom plate of the second plurality of capacitors is electrically coupled with the second input voltage V inn , and each top plate of the first and second pluralities of capacitors is electrically coupled with the common mode voltage V cm during a sampling phase.

9. The system of claim 8 , wherein each top plate of the first and second pluralities of capacitors is disconnected from the common mode voltage V cm and each bottom plate of the first and second pluralities of capacitors is electrically coupled with the common mode voltage V cm during a first conversion cycle.

10. The system of claim 9 , wherein a determination is made whether to collapse a section during each of multiple subsequent conversion cycles, the determination being based on a comparison between the conversion residue of the most significant bit (MSB) of the section and the least significant bit (LSB) weight of the section.

11. A system, comprising:
an analog input port;
a digital output port; and
a successive approximation register (SAR) analog-to-digital converter (ADC), the SAR ADC including:
a voltage comparator V d having a first input, a second input, and an output;
a first plurality of capacitors C p [0:n] that are coupled with the analog input port and each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with a common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a first input voltage V inp , a reference voltage V ref , the common mode voltage V cm , and ground, wherein the common mode voltage V cm is equal to one-half of the reference voltage V ref , and wherein the first plurality of capacitors C p [0:n] includes 8 capacitors C p [0:7];
a second plurality of capacitors C n [0:n] that are coupled with the analog input port and each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with the common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a second input voltage V inn , the reference voltage V ref , the common mode voltage V cm , and ground, wherein the second plurality of capacitors C n [0:n] includes 8 capacitors C n [0:7], wherein the first and second pluralities of capacitors together represent two 4-bit sections C[0:7], and wherein the two 4-bit sections include two most significant bits (MSBs) C[3] and C[7], each MSB having three corresponding least significant bits (LSBs) C[2:0] and C[6:4], respectively; and
a SAR controller coupled between the output of the voltage comparator V d and the digital output port, wherein the SAR controller is configured to implement a collapsible SAR algorithm that performs a comparison of the conversion residue to the mid-code of the remaining least significant bits (LSBs).

12. The system of claim 11 , wherein the collapsible SAR algorithm determines the most significant bit (MSB) value of the remaining least significant bits (LSBs) based on the polarity of the comparison.

13. A system, comprising:
an analog input port;
a digital output port; and
a successive approximation register (SAR) analog-to-digital converter (ADC), the SAR ADC including:
a voltage comparator V d having a first input, a second input, and an output;
a first plurality of capacitors C p [0:n] that are coupled with the analog input port and each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V d , wherein each top plate is also switchably electrically coupled with a common mode voltage V cm , and wherein each bottom plate is switchably electrically coupled between a first input voltage V inp , a reference voltage V ref , the common mode voltage V cm , and ground, wherein the common

Assignees

• Avnera Corp

Inventors

• Wen Jianping
• Link Garry
• Lee Wai Laing

Classifications

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/0682

  using a differential network structure, i.e. symmetrical with respect to ground · CPC title

• H03M1/403

  using switched capacitors · CPC title

• H03M1/0692

  using a diminished radix representation, e.g. radix 1.95 · CPC title

• H03M1/804

  with charge redistribution · CPC title