Semiconductor device

Patent metadata

Field	Value
Publication number	US-10135337-B2
Application number	US-201715491875-A
Country	US
Kind code	B2
Filing date	Apr 19, 2017
Priority date	Oct 23, 2012
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

Provided is a semiconductor device including a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

First claim

What is claimed is:

1. A semiconductor device including a DC/DC converter circuit, the semiconductor device comprising:
a substrate having a main surface including a first region, a second region, and a third region arranged between the first region and the second region;
a first frame formed in the first region over the substrate;
a second frame formed in the second region over the substrate;
a third frame formed in the third region over the substrate;
a compound semiconductor substrate having a first surface and a second surface opposite the first surface,
wherein the compound semiconductor substrate has a first side, a second side opposite the first side, and a third side between the first side and the second side, and
wherein the compound semiconductor substrate is mounted on the third frame so as to face the second surface to the main surface of the substrate;

a first pad formed over the first surface and arranged along the first side;
a second pad formed over the first surface and arranged along the second side;
a third pad formed over the first surface and arranged between the first pad and the second pad;
a first transistor constituting a part of the DC/DC converter circuit and formed in the compound semiconductor substrate; and
a second transistor constituting a part of the DC/DC converter circuit and formed in the compound semiconductor substrate,
wherein the first transistor includes a first gate electrode, a first gate insulating film, a first source electrode and a first drain electrode and is arranged between the first pad and the third pad in plan view,
wherein the second transistor includes a second gate electrode, a second gate insulating film, a second source electrode and a second drain electrode and is arranged between the second pad and the third pad in a planar view,
wherein the first drain electrode is connected to the first pad,
wherein the first source electrode and the second drain electrode are connected to the third pad,
wherein the second source electrode is connected to the second pad,
wherein the first frame is arranged along the first side of the compound semiconductor substrate,
wherein the second frame is arranged along the second side of the compound semiconductor substrate,
wherein the third frame has a first portion, over which the compound semiconductor substrate is arranged, and a second portion, which is exposed from the compound semiconductor substrate, and is arranged along the third side,
wherein the first pad is connected to the first frame through a first clip,
wherein the second pad is connected to the second frame through a second clip, and
wherein the third pad is connected to the second portion of the third frame through a third clip.

2. A semiconductor device according to the claim 1 ,
wherein the compound semiconductor substrate has a GaN layer and an AlGaN layer provided over the GaN layer.

3. A semiconductor device according to the claim 2 ,
wherein a part of the first gate electrode is located within a recess formed in the compound semiconductor substrate, and
wherein the second gate electrode has a planer gate structure.

4. A semiconductor device according to the claim 3 ,
wherein the first transistor is a normally-off type, and
wherein the second transistor is a normally-on type.

5. A semiconductor device according to the claim 2 ,
wherein each of the first, second and third clips includes copper.

6. A semiconductor device according to the claim 5 ,
wherein the first, second and third pad are respectively bonded to the first, second and third clips by solder.

Assignees

• Renesas Electronics Corp

Inventors

• Nega Ryohei
• Miura Yoshinao

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title