Method for fabricating a hybrid land grid array connector

Patent metadata

Field	Value
Publication number	US-10135162-B1
Application number	US-201715842962-A
Country	US
Kind code	B1
Filing date	Dec 15, 2017
Priority date	Sep 28, 2017
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

Embodiments of the present invention include a method for fabricating a hybrid land grid array connector and the resulting structures. A body is provided. The body includes a first plurality of holes and a second plurality of holes. A conductive layer is deposited on the top and bottom surfaces of the body and the wall surfaces of the first plurality of holes resulting in the top and bottom surfaces being electrically common. The conductive layer is removed from the wall surfaces of a first subset of the first plurality of holes. A portion of the conductive layer is removed from the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.

First claim

What is claimed is:

1. A method, the method comprising:
providing a body for a hybrid land grid array connector, wherein the body includes a first plurality of holes and a second plurality of holes;
depositing a conductive layer on a top surface of the body, a bottom surface of the body, and wall surfaces of the first plurality of holes, wherein the top surface of the body is electrically common with the bottom surface of the body;
removing the conductive layer from wall surfaces of a first subset of the first plurality of holes; and
removing a portion of the conductive layer on the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.

2. The method of claim 1 , further comprising:
stitching a plurality of spring contacts into the first plurality of holes, wherein:
the plurality of spring contacts stitched into the first subset of the first plurality of holes are electrically isolated from one another; and
the plurality of spring contacts stitched into a second subset of the first plurality of holes are electrically common with, at least, one another, the conductive layer on the top surface of the body, and the conductive layer on the bottom surface of the body.

3. The method of claim 1 , wherein a subtractive photolithography process is used to remove the conductive layer from the wall surfaces of the first subset of the first plurality of holes and the area surrounding the first subset of the first plurality of holes.

4. The method of claim 1 , further comprising:
depositing a material into a second subset of the first plurality of holes.

5. The method of claim 4 , wherein the material is a dielectric material.

6. The method of claim 1 , wherein the step of depositing a conductive layer on a top surface of the body, a bottom surface of the body, and wall surfaces of the first plurality of holes further comprises:
depositing the conductive layer on wall surfaces of the second plurality of holes.

7. The method of claim 1 , further comprising:
stitching a conductive post into each of the second plurality of holes, wherein the conductive post provides an electrical connection between the conductive layer on the top surface of the body and the conductive layer on the bottom surface of the body.

Assignees

• IBM

Inventors

• Hejase Jose A
• Becker Wiren D
• Dreps Daniel
• Chun Sungjun
• Beaman Brian

Classifications

• H05K2201/10719

  Land grid array [LGA] · CPC title

• H05K2201/09954

  More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads · CPC title

• H01R12/526 Primary

  the printed circuits being on the same board (with plated through holes H05K3/42) · CPC title

• H05K3/3426

  characterised by the leads · CPC title

• H05K2201/10378

  Interposers · CPC title