Package vias for radio frequency antenna connections

Patent metadata

Field	Value
Publication number	US-9252077-B2
Application number	US-201314037213-A
Country	US
Kind code	B2
Filing date	Sep 25, 2013
Priority date	Sep 25, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

Via are described for radio frequency antenna connections related to a package. In one example, a package has a package substrate, a die attached to the package substrate, and a conductive via from the package substrate to an external surface of the package to make a radio frequency connection between the antenna and the package substrate.

First claim

What is claimed is:

1. A package comprising:
a package substrate;
a die attached to the package substrate;
a molding compound over the die and the package substrate forming the external surface of the package;
an antenna on the external surface of the package; and
a conductive via from the package substrate to the external surface of the package to make a radio frequency connection between the antenna and the package substrate,
wherein the via has parallel concentric conducting paths isolated by a dielectric.

2. The package of claim 1 , further comprising the antenna on the external surface of the package and wherein the conductive via connects to the antenna.

3. The package of claim 1 , wherein the die attachment to the package substrate includes a radio frequency connection through the package substrate to the conductive via.

4. The package of claim 1 , wherein the package substrate is formed over the die and the molding compound.

5. The package of claim 4 , further comprising:
a metal interconnect layer over the molding compound; and
the antenna formed over the metal interconnect layer.

6. The package of claim 5 , further comprising a dielectric layer between the metal interconnect layer and the antenna.

7. The package of claim 4 , wherein the conductive via is a through-mold via extending through the molding compound.

8. The package of claim 1 , wherein the conductive via extends through the die and connects to the package substrate using connectors of the die.

9. The package of claim 1 , further comprising a second conductive via through the die to make a radio frequency connection between the antenna and the die.

10. A package comprising:
a die;
molding compound over the die and the package substrate forming the external surface of the package;
an antenna over the molding compound on the external surface of the package; and
a via between the die and the antenna through the molding compound to couple signals between the antenna and the die,
wherein the via has parallel concentric conducting paths isolated by a dielectric.

11. The package of claim 10 , further comprising additional vias between the die and the antenna wherein a first subset of the additional vias carry a signal of one polarity and a second subset of the additional vias carry a signal of the other polarity.

12. The package of claim 10 , wherein the via is copper filled.

13. The package of claim 10 , wherein the die is an RF power amplifier.

14. The package of claim 10 , wherein the antenna is a copper line on a substrate over the molding compound.

15. The package of claim 10 , further comprising a substrate, the die being electrically connected to the substrate and wherein the via is coupled between the antenna and the substrate and the substrate connects the via to the die.

16. The package of claim 15 , further comprising a second via through the die to connect the via to the substrate.

17. The package of claim 16 , wherein the second via is a through-silicon via.

Assignees

• Molzer Wolfgang
• Goetz Edmund
• Mahnkopf Reinhard
• Memmler Bernd
• Intel Corp

Inventors

• Molzer Wolfgang
• Goetz Edmund
• Mahnkopf Reinhard
• Memmler Bernd

Classifications

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2128

  Coaxial through-semiconductor vias · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/874

  On different surfaces · CPC title