Transistor devices, memory cells, and arrays of memory cells

Patent metadata

Field	Value
Publication number	US-10134916-B2
Application number	US-201213595832-A
Country	US
Kind code	B2
Filing date	Aug 27, 2012
Priority date	Aug 27, 2012
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate dielectric is between the first gate and the channel region. A second gate is proximate the channel region. A programmable material is between the second gate and the channel region. The programmable material includes at least one of a) a multivalent metal oxide portion and an oxygen-containing dielectric portion, or b) a multivalent metal nitride portion and a nitrogen-containing dielectric portion. Memory cells and arrays of memory cells are disclosed.

First claim

The invention claimed is:

1. A transistor device comprising: a pair of source/drain regions having a channel region there-between;
a first gate on a first side of the channel region, the first gate being patterned into a first gate line extending along a first direction; a gate dielectric between the first gate and the channel region;
a second gate on an opposing second side of the channel region, the second gate being patterned into a second gate line extending along a second direction that crosses the first direction; a layer of programmable material that extends continuously in the second direction along the entire length of the second gate, and between the second gate and the channel region, the programmable material comprising at least one of
a) a multivalent metal oxide portion comprising one or more of SrxRuyOz, RuOx, InxSnyOz, MgO, BaTiO3, ZrOx and CaMnO3 doped with La, Sr or Sm, and an oxygen-containing dielectric portion, or
b) a multivalent metal nitride portion and a nitrogen-containing dielectric portion; and wherein the multivalent portion of the programmable material is directly against the second gate.

2. The transistor device of claim 1 wherein the dielectric portion of the programmable material is more proximate the channel region than is the multivalent metal oxide portion, and wherein threshold voltage of the transistor device relative to operation of the first gate may be changed by applying a first voltage having a first polarity across the first and second gates and reversibly changed by applying a second voltage having a second polarity across the first and second gates, the second polarity being opposite to the first polarity.

3. The transistor device of claim 1 wherein the dielectric portion of the programmable material is directly against the channel region.

4. The transistor device of claim 1 wherein the multivalent portion of the programmable material is directly against the dielectric portion of the programmable material.

5. The transistor device of claim 1 wherein the channel region has opposite sides, the first gate being proximate one of the opposite sides and the second gate being proximate the other of the opposite sides.

6. The transistor device of claim 1 wherein no portion of the second gate is directly against the channel region.

7. The transistor device of claim 1 wherein the programmable material comprises the multivalent metal oxide portion and the oxygen-containing dielectric portion.

8. The transistor device of claim 7 wherein the multivalent metal oxide portion comprises one or more of barium, ruthenium, strontium, titanium, calcium, manganese, praseodymium, lanthanum and samarium.

9. The transistor device of claim 7 wherein the oxygen-containing dielectric portion comprises one or more oxides of hafnium, zirconium, yttrium, and aluminum.

10. The transistor device of claim 7 wherein the multivalent metal oxide portion comprises one or more of barium, ruthenium, strontium, titanium, calcium, manganese, praseodymium, lanthanum and samarium; and the oxygen-containing dielectric portion comprises one or more oxides of hafnium, zirconium, yttrium, and aluminum.

11. The transistor device of claim 7 wherein the multivalent metal oxide portion comprises calcium, manganese, and oxygen; and the oxygen-containing dielectric portion comprises one or more oxides of hafnium, zirconium, yttrium, and aluminum.

12. The transistor device of claim 11 wherein the oxygen-containing dielectric portion consists essentially of one or more of oxides of hafnium, zirconium, yttrium, and aluminum.

13. The transistor device of claim 1 wherein the programmable material comprises the multivalent metal nitride portion and the nitrogen-containing dielectric portion.

14. The transistor device of claim 13 wherein the multivalent metal nitride portion comprises at least one of aluminum and gallium.

15. The transistor device of claim 13 wherein the nitrogen-containing dielectric portion comprises one or more nitrides of hafnium, titanium, zirconium, yttrium, and tantalum.

16. The transistor device of claim 13 wherein the multivalent metal nitride portion comprises at least one of aluminum and gallium, and the nitrogen-containing dielectric portion comprises one or more nitrides of hafnium, titanium, zirconium, yttrium, and tantalum.

17. A memory cell comprising:
a pair of source/drain regions having a channel region there-between;
a first gate on a first side of the channel region, the first gate being comprised by a first gate line that extends along a first direction;
a gate dielectric between the first gate and the channel region;
a second gate on an opposing second side of the channel region, the second gate being comprised by a second line that extends along a second direction that orthogonally crosses the first direction; and
a layer of programmable material that extends continuously in the second direction along the entire length of the second gate, and between the second gate and the channel region, the line of programmable material extending along the second direction and comprising a multivalent metal nitride portion and a nitrogen-containing dielectric portion, the multivalent metal nitride portion being in direct physical contact with the second gate.

18. The memory cell of claim 17 wherein the dielectric portion of the programmable material is more proximate the channel region than is the multivalent metal nitride portion, and wherein threshold voltage of a transistor constituting the pair of source/drain regions, the channel region, the first gate, and the gate dielectric may be changed by applying a first voltage having a first polarity across the first and second gates and reversibly changed by applying a second voltage having a second polarity across the first and second gates, the second polarity being opposite to the first polarity.

19. An array of memory cells, comprising:
a plurality of first gate lines over one side of respective channel regions, gate dielectric being between the first gate lines and the one side of the channel regions and being directly against the first gate lines, the channel regions being between respective pairs of source/drain regions;
a plurality of second gate lines crossing the first gate lines on a side of the respective channel regions opposite the one side, programmable material between the second gate lines and the channel regions, the programmable material comprising at least one of
a) a multivalent metal oxide portion comprising one or more of SrxRuyOz, RuO x , InxSnyOz, MgO, BaTiO3, ZrOx and CaMnO3 doped with La, Sr or Sm, and an oxygen-containing dielectric portion, or
b) a multivalent metal nitride portion and a nitrogen-containing dielectric portion; and
wherein the multivalent metal portion of the programmable material is directly against the second gate lines and is patterned into lines of multivalent metal material that extend continuously along the entire length of the second gate lines.

20. The array of claim 19 wherein the lines of the multivalent material have lateral outlines which are the same as those of the second gate lines in one cross-section.

21. The array of claim 19 wherein the dielectric portions of the programmable material are formed in a plurality of lines which respectively parallel respective of the second gate lines.

22. The array of claim 21 wherein the lines of the dielectric portions have lateral outlines which are the same as those of the second gate lines in one

Assignees

• Ramaswamy D V Nirmal
• Sandhu Gurtej S
• Micron Technology Inc

Inventors

• Ramaswamy D V Nirmal
• Sandhu Gurtej S

Classifications

• H01L29/7887 Primary

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic

• H10D30/687 Primary

  having more than two programming levels · CPC title

• H10B41/30

  characterised by the memory core region · CPC title