Organic light emitting diode display having thin film transistor substrate using oxide semiconductor

Patent metadata

Field	Value
Publication number	US-10134877-B2
Application number	US-201615094572-A
Country	US
Kind code	B2
Filing date	Apr 8, 2016
Priority date	Jul 30, 2013
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A method for manufacturing an organic light emitting diode (OLED) display can include forming a gate electrode on a substrate, forming a semiconductor layer by depositing a gate insulating layer and an oxide semiconductor material and patterning the oxide semiconductor material, forming an etch stopper on a central portion of the semiconductor layer, conducting a plasma treatment using the etch stopper as a mask to conductorize portions of the semiconductor layer exposed by the etch stopper for defining a channel area, a source area and a drain area, and forming a source electrode contacting portions of the conductorized source area and a drain electrode contacting portions of the conductorized drain area.

First claim

What is claimed is:

1. A method for manufacturing an organic light emitting diode (OLED) display, the method comprising:
forming a gate electrode on a substrate;
forming a semiconductor layer having a source area, a drain area and a channel area between the source area and the drain area by depositing a gate insulating layer and an oxide semiconductor material and patterning the oxide semiconductor material;
forming an etch stopper on the semiconductor layer and the gate insulation layer to expose a portion of the source area and a portion of the drain area of the semiconductor layer;
conducting a plasma treatment using the etch stopper as a mask to conductorize the portion of the source area and the portion of the drain area of the semiconductor layer exposed by the etch stopper for defining the channel area, the source area and the drain area; and
forming a source electrode contacting the portion of the conductorized source area and a drain electrode contacting the portion of the conductorized drain area,
wherein the forming the source electrode and the drain electrode includes:
depositing a first metal layer and a second metal layer sequentially on the etch stopper;
patterning the second metal layer with an wet etching method; and
patterning the first metal layer with a dry etching method using the patterned second metal layer as a mask,

wherein the source electrode contacts a surface of the portion of the source area that is apart from the channel area with a first predetermined distance,
wherein the drain electrode contacts a surface of the portion of the drain area that is apart from the channel area with a second predetermined distance, and
wherein the etch stopper includes a first portion disposed on a portion of the gate insulation layer and a portion of the source area at a position in which the first portion overlaps the gate electrode, a second portion disposed on the channel area at a position in which the second portion overlaps the gate electrode, and a third portion disposed on another portion of the gate insulation layer and a portion of the drain area at a position in which the third portion overlaps the gate electrode.

2. The method according to claim 1 , wherein the step of forming the etch stopper includes:
depositing an insulating layer on the semiconductor layer; and
forming a source area hole exposing the source area and a drain area hole exposing the drain area by patterning the insulating layer using a mask.

3. The method according to claim 1 , wherein the first metal layer and the second metal layer of the source and drain electrodes have a same shape and size, respectively.

4. The method according to claim 1 , wherein the step of conducting the plasma treatment includes reducing an oxygen content in the exposed portions of the semiconductor layer.

5. The method according to claim 1 , wherein the step of conducting the plasma treatment includes aligning a first end of the etch stopper with a boundary between the channel area and the source area and a second end of the etch stopper with a boundary between the channel area and the drain area.

6. The method according to claim 1 , wherein the conductorized source and drain areas extend from a top surface of the semiconductor layer to a bottom surface of the semiconductor layer.

7. The method according to claim 1 , wherein the source electrode is disposed on the first portion of the etch stopper and the conductorized source area exposed between the first portion of the etch stopper and the second portion of the etch stopper.

8. The method according to claim 7 , wherein the drain electrode is disposed on the third portion of the etch stopper and the conductorized drain area exposed between the second portion of the etch stopper and the third portion of the etch stopper.

9. The method according to claim 1 , wherein the gate electrode overlaps with the source area and the drain area and extends past outer edges of the source area and the drain area.

10. The method according to claim 1 , wherein the first metal layer is thinner than the second metal layer.

Assignees

• Lg Display Co Ltd

Inventors

• Hong Sungjin
• Ahn Byungchul
• Koh Youngju
• Nam Woojin
• Tani Ryosuke

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H01L27/3262

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic

• H01L2227/323

  Electricity · mapped topic