Porous silicon post processing

Patent metadata

Field	Value
Publication number	US-10134837-B1
Application number	US-201715638874-A
Country	US
Kind code	B1
Filing date	Jun 30, 2017
Priority date	Jun 30, 2017
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A semiconductor on insulator (SOI) device may include a semiconductor handle substrate. The semiconductor hand may include a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer. The SOI may also include an insulator layer on the etch stop layer. The SOI may further include a device semiconductor layer on the insulator layer.

First claim

What is claimed is:

1. A semiconductor on insulator (SOI) device, comprising:
a semiconductor handle substrate comprising a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer;
an insulator layer on the etch stop layer;
a bulk semiconductor layer between the insulator layer and the etch stop layer; and
a device semiconductor layer on the insulator layer.

2. The device of claim 1 , in which the etch stop layer comprises implanted germanium.

3. The device of claim 1 , in which the etch stop layer comprises a trap rich layer.

4. The device of claim 1 , in which the device semiconductor layer comprises radio frequency (RF) switch devices.

5. The device of claim 1 , in which the etch stop layer comprises a counter-doped layer.

6. The device of claim 5 , further comprising a trap rich layer as the bulk semiconductor layer between the insulator layer and the counter-doped layer.

7. The device of claim 1 , integrated into an RF front end module, the RF front end module incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

8. A semiconductor on insulator (SOI) device, comprising:
an insulator layer having a backside surface on a semiconductor handle substrate;
a device semiconductor layer on a front-side surface of the insulator layer; and
the semiconductor handle substrate including an etch stop layer proximate the insulator layer and a bulk semiconductor layer between the insulator layer and the etch stop layer, the semiconductor handle substrate comprising means for reducing radio frequency (RF) harmonics contacting the etch stop layer.

9. The device of claim 8 , in which the etch stop layer comprises implanted germanium.

10. The device of claim 8 , in which the etch stop layer comprises a trap rich layer.

11. The device of claim 8 , in which the device semiconductor layer comprises radio frequency (RF) switch devices.

12. The device of claim 8 , in which the etch stop layer comprises a counter-doped layer.

13. The device of claim 8 , integrated into an RF front end module, the RF front end module incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

Assignees

• Qualcomm Inc

Inventors

• Fanelli Stephen Alan
• Hammond Richard

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P50/613 Primary

  of Group IV materials · CPC title