Integrated trench capacitor

Patent metadata

Field	Value
Publication number	US-10134830-B2
Application number	US-201615264147-A
Country	US
Kind code	B2
Filing date	Sep 13, 2016
Priority date	Sep 13, 2016
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A deep trench capacitor and a method for providing the same in a semiconductor process are disclosed. The method includes forming a plurality of deep trenches in a first region of a semiconductor wafer, the first region having well doping of a first type. A dielectric layer is formed on a surface of the plurality of deep trenches and a doped polysilicon layer is deposited to fill the plurality of deep trenches, with the doped polysilicon being doped with a dopant of a second type. Shallow trench isolation is formed overlying the dielectric layer at an intersection of the dielectric layer with the surface of the semiconductor wafer.

First claim

What is claimed is:

1. A method for providing a deep trench capacitor in a semiconductor process, the method comprising:
forming a plurality of deep trenches in a first region of a semiconductor wafer, the first region having well doping of a first type;
for each deep trench, forming first and second dielectric layer portions on respective first and second sidewall surfaces;
depositing a doped polysilicon layer to fill the plurality of deep trenches, the doped polysilicon being doped with a dopant of a second type;
for each deep trench, removing portions of said doped polysilicon layer, thereby forming a first shallow trench over said first dielectric layer portion and a second shallow trench over said second dielectric layer portion; and
filling said first and second trenches with oxide, thereby forming a first shallow trench isolation that extends from the first dielectric layer portion to a top surface of the semiconductor wafer, and a second shallow trench isolation that extends from the second dielectric layer portion to said top surface.

2. The method as recited in claim 1 wherein the first type of dopants are N-type and the second type of dopants are P-type and the substrate is doped with P-type dopants.

3. The method as recited in claim 1 wherein the elements of forming the plurality of deep trenches, forming the dielectric layer, and depositing the doped polysilicon layer are part of a modular flow that can be added to a process flow when a capacitor is desired without changing elements outside the modular flow.

4. The method as recited in claim 1 further comprising, prior to forming the plurality of deep trenches, forming the first region.

5. The method as recited in claim 4 wherein forming the first region comprises forming a buried layer having doping of the first type in an epitaxial layer, implanting a dopant of the first type in the epitaxial layer overlying the buried layer and thermally driving the doping deeper into the semiconductor wafer to form a heavily doped well.

6. The method as recited in claim 5 wherein forming the first region is part of a baseline flow for the semiconductor process.

7. The method as recited in claim 1 wherein forming the dielectric layer comprises growing a thermal oxide.

8. The method as recited in claim 7 wherein forming the dielectric layer further comprises depositing a nitride layer over the thermal oxide.

9. The method as recited in claim 8 wherein forming the dielectric layer further comprises performing a wet oxidation of the nitride layer to form an oxynitride layer over the nitride layer.

10. The method as recited in claim 1 further comprising providing a source/drain implant of the first type of dopants to the first region and providing source/drain implants of the second type of dopants to the doped polysilicon layer.

11. The method as recited in claim 10 further comprising providing contacts to the first region and to the polysilicon layer.

12. The method as recited in claim 1 , further comprising performing chemical-mechanical polishing (CMP) on the semiconductor wafer after filling said shallow trenches, thereby planarizing the oxide.

13. The method as recited in claim 1 wherein the first type of dopants and the second type of dopants are both N-type dopants.

Assignees

• Texas Instruments Inc

Inventors

• Hu Binghua
• Kawahara Hideaki
• Pendharkar Sameer P

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/6304

  Formation by oxidation, e.g. oxidation of the substrate · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title