Memory device

Patent metadata

Field	Value
Publication number	US-10134752-B2
Application number	US-201615393775-A
Country	US
Kind code	B2
Filing date	Dec 29, 2016
Priority date	Jun 22, 2016
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

First claim

What is claimed is:

1. A memory device comprising:
a substrate;
a plurality of gate electrode layers stacked on the substrate;
a plurality of channel layers penetrating the plurality of gate electrode layers;
a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, the gate insulating layer including a plurality of vertical parts and a horizontal part, the plurality of vertical parts surrounding respective ones of the plurality of channel layers, the horizontal part being below the plurality of gate electrode layers and extending parallel to a top surface of the substrate; and
a common source line on the substrate adjacent to the plurality of gate electrode layers, the common source line including a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to the top surface of the substrate.

2. The memory device of claim 1 , wherein
the substrate includes a source region under the common source line, and
the source region includes an uneven surface in the first direction.

3. The memory device of claim 1 , wherein
the substrate includes a plurality of supporting regions protruding toward the common source line, and
the plurality of supporting regions are separated from each other in the first direction.

4. The memory device of claim 3 , wherein
the first part of the common source line is on the plurality of supporting regions, and
a width of the plurality of supporting regions is larger than a width of the common source line in a second direction that is perpendicular to the first direction.

5. The memory device of claim 4 , wherein a height of the first part is less than a height of the second part.

6. The memory device of claim 3 , wherein top surfaces of the plurality of supporting regions contact a bottom surface of the first part of the common source line.

7. The memory device of claim 1 , wherein the horizontal part of the gate insulating layer extends from the plurality of vertical parts of the gate insulating layer and connects at least some of the plurality of vertical parts to each other.

8. The memory device of claim 1 , further comprising:
a horizontal channel layer on the substrate, wherein
the horizontal channel layer extends parallel to the top surface of the substrate, below the plurality of the gate electrode layers, and
at least some of the plurality of channel layers are connected to each other by the horizontal channel layer.

9. The memory device of claim 8 , wherein the plurality of channel layers are connected to the substrate by the horizontal channel layer.

10. The memory device of claim 8 , wherein the horizontal part of the gate insulating layer is on a top surface of the horizontal channel layer.

11. The memory device of claim 8 , wherein the substrate includes at least one void below the horizontal channel layer.

12. The memory device of claim 8 , wherein the substrate includes an impurity region adjacent to the horizontal channel layer, and the impurity region includes carbon.

13. The memory device of claim 1 , further comprising:
a buried insulating layer on the substrate, wherein
the plurality of channel layers surround the buried insulating layer, and
the buried insulating layer extends vertical into the substrate a greater distance compared to the plurality of channel layers.

14. A memory device comprising:
a substrate;
a plurality of gate structures on the substrate, each of the plurality of gate structures including a plurality of gate electrode layers and a plurality of insulating layers that are alternately stacked on the substrate;
a plurality of channel layers extending in a direction vertical to a top surface of the substrate, the plurality of channel layers penetrating the plurality of gate structures, and the plurality of channel layers being disposed in a plurality of channel holes, respectively;
a common source line extending along a first direction parallel to the top surface of the substrate, and disposed on the substrate between the plurality of gate structures;
a charge storage layer including vertical parts and horizontal parts,
the vertical parts outside respective ones of the plurality of channel layers of each of the plurality of gate structures, and
the horizontal parts extending from the vertical parts to below each of the plurality of gate structures; and

a horizontal channel layer below the horizontal parts of the charge storage layer, the horizontal channel layer connecting the plurality of channel layers to each other and contacting the substrate,
wherein the common source line includes a first part and a second part that have different heights and are alternately arranged in the first direction.

15. The memory device of claim 14 , wherein the vertical parts of the charge storage layer are connected to each other by the horizontal parts of the charge storage layer.

16. The memory device of claim 14 , wherein the horizontal parts of the charge storage layer is only on a top surface of the horizontal channel layer.

17. The memory device of claim 14 , wherein
the substrate includes an impurity region below the horizontal channel layer, and
the impurity region includes carbon.

18. A memory device comprising:
a substrate; and
a stack structure on the substrate,
the stack structure including
a gate insulating layer that includes a horizontal part extending parallel to a top surface of the substrate and a plurality of vertical parts that are spaced apart from each other and extend vertical above the top surface of the substrate,
a plurality of channel layers surrounded by the plurality of vertical parts of the gate insulating layer and extending vertical to the top surface of the substrate,
a plurality of gate electrode layers and insulating layers alternately stacked on top of each other on the horizontal part of the gate insulating layer,
a plurality of strings that are defined by the gate insulating layer, the plurality of channel layers and the plurality of gate electrode layers, and each include a plurality of memory cells stacked on top of each other between a ground selection transistor and a string selection transistor, and
a horizontal channel layer connecting at least some of the plurality of channel layers included in different strings to each other and extending between a lower surface of the horizontal part of the gate insulating layer and the top surface of the substrate,

wherein the substrate includes an impurity region adjacent to the horizontal channel layer, and the impurity region includes carbon.

19. The memory device of claim 18 , further comprising:
a common source line on the substrate adjacent to the stack structure, wherein
the substrate includes a source region under the common source line, and
the source region includes an uneven top surface.

20. The memory device of claim 18 , wherein the substrate includes at least one void below the horizontal channel layer.

Assignees

• Kim Kwang Soo
• Kang Shin Hwan
• Jang Jae Hoon
• Kanamori Kohji
• Samsung Electronics Co Ltd

Inventors

• Kim Kwang Soo
• Kang Shin Hwan
• Jang Jae Hoon
• Kanamori Kohji

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11556

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title