Array substrate, testing method, display panel and display apparatus

US10134316B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10134316-B2
Application numberUS-201615004843-A
CountryUS
Kind codeB2
Filing dateJan 22, 2016
Priority dateApr 1, 2015
Publication dateNov 20, 2018
Grant dateNov 20, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides an array substrate, a testing method, a display panel and a display apparatus. The array substrate includes: multiple gate wires and data wires intersecting with each other to divide multiple sub-pixel regions, where the sub-pixels corresponding to each of the data wires form a column of the sub-pixels, and M neighboring columns of the sub-pixels form a sub-pixel group; multiple switch units, where a first end of each of the switch units is electrically connected to one of the data wires; and multiple testing ends, each of which is electrically connected to second ends of the switch units. In such configuration, at least two switch units are electrically connected to the data wires corresponding to i th columns of the sub-pixels in at least two alternately arranged sub-pixel groups, respectively. Accordingly, impacts to voltage of common electrodes may be avoided and testing effect may be improved.

First claim

Opening claim text (preview).

What is claimed is: 1. An array substrate, comprising: a plurality of sub-pixels arranged in rows and columns of a matrix form, wherein the plurality of sub-pixels each is associated with one of four colors: red, green, blue and white; a plurality of gate wires arranged in row direction, wherein the plurality of gate wires each is electrically connected to an associated sub-pixel row of the plurality of sub-pixels; a plurality of data wires arranged in column direction, wherein the plurality of data wires each is electrically connected to an associated sub-pixel column of the plurality of sub-pixels; a control end providing a control signal; a plurality of testing ends providing testing signals; and a plurality of switch units each associated with one sub-pixel column, and each comprising a first end, a second end and a control end, wherein the first end of each switch unit is electrically connected to the associated data wire, wherein the control end of each switch unit is electrically connected to the control signal from the control end; wherein the plurality of sub-pixels is divided into K sub-pixel groups B k , each comprising M sub-pixel columns (B k1 , B k2 , . . . , B kM ), wherein K is an integer not less than 4, M is an integer not less than 2, and k takes each integer value in a range from 1 to K, inclusively, and wherein two sub-pixels of the plurality of sub-pixels in one row and from two adjacent columns are associated with two different of the four colors; wherein the second ends of two switch units associated with two sub-pixel columns (B ji , B (j+2)i ) are electrically connected to a same testing end; and wherein the second ends of two switch units associated with two sub-pixel columns (B ji , B (j+1)i ) are electrically connected to two different testing ends, wherein j takes each integer value in a range from 1 to K−2, inclusively, and i takes each integer value in a range from 1 to M, inclusively. 2. The array substrate according to claim 1 , wherein, M is an odd number, and wherein, testing signals supplied from the two testing ends corresponding to the two i th columns, which respectively belong to the j th group and the (j+1) th group, have opposite polarities. 3. The array substrate according to claim 1 , wherein the plurality of sub-pixels form 2×2 blocks each having four sub-pixels of the four colors, when M is 2. 4. The array substrate according to claim 1 , wherein the plurality of sub-pixels form 3×1 blocks each having three sub-pixels of three different of the four colors, when M is 3. 5. The array substrate according to claim 1 , wherein the plurality of switch units comprises switches with a same conductive type. 6. The array substrate according to claim 1 , further comprising: a plurality of touch-control electrodes and a plurality of touch-control electrode lead wires, where the touch-control electrodes are formed by dividing common electrodes, and each of the touch-control electrode lead wires is electrically connected to one of the touch-control electrodes, wherein a common voltage is supplied to the touch-control electrodes at a display stage, and a touch-control detecting signal is supplied to the touch-control electrodes at a touch-control stage. 7. The array substrate according to claim 1 , further comprising: a substrate; a first conductive layer formed on any surface of the substrate, wherein the first conductive layer comprises a gate; a gate dielectric layer formed on the first conductive layer; a semiconductor layer formed on the gate dielectric layer wherein the semiconductor layer comprises an active region; and a second conductive layer containing the plurality of data wires formed on the semiconductor layer, wherein the second conductive layer comprises a source and a drain, and wherein the gate, the active region, the source and the drain form a thin-film transistor in each of the sub-pixel of the plurality of sub-pixels. 8. A display panel, comprising the array substrate according to claim 1 . 9. A display apparatus, comprising the display panel according to claim 8 .

Assignees

Inventors

Classifications

  • Arrangements or methods for testing or calibrating a device · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • G09G3/006Primary

    Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

  • Physics · mapped topic

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What does patent US10134316B2 cover?
The present disclosure provides an array substrate, a testing method, a display panel and a display apparatus. The array substrate includes: multiple gate wires and data wires intersecting with each other to divide multiple sub-pixel regions, where the sub-pixels corresponding to each of the data wires form a column of the sub-pixels, and M neighboring columns of the sub-pixels form a sub-pixel…
Who is the assignee on this patent?
Shanghai Tianma Micro Elect Co, Tianma Micro Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/006. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 20 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).