Active matrix substrate including signal terminals additional signal terminals and switching elements for testing the active matrix substrate

US9614001B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9614001-B2
Application numberUS-201113807021-A
CountryUS
Kind codeB2
Filing dateJun 22, 2011
Priority dateJun 28, 2010
Publication dateApr 4, 2017
Grant dateApr 4, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An active matrix substrate includes a plurality of bus lines ( 1, 2 ) provided in a pixel region, a plurality of signal terminals ( 5 ) provided in a connection terminal region (K), connection lines ( 3 ), additional signal terminals ( 11 ), test lines ( 8 ), and switching elements ( 4 ). The switching elements ( 4 ) are divided into a plurality of groups, and can control connections between the bus lines and the test lines ( 8 ) on a group basis, and connection elements ( 12 ) that each include a diode or a switching element and connect the signal terminals ( 5 ) to each other are provided in the connection terminal region (K).

First claim

Opening claim text (preview).

The invention claimed is: 1. An active matrix substrate comprising: a plurality of bus lines provided in a pixel region; a plurality of signal terminals that input a driving signal to each of the bus lines, the plurality of signal terminals being provided in a connection terminal region situated outside the pixel region; connection lines that connect the plurality of signal terminals to the bus lines; additional signal terminals that input a signal to the bus lines through different paths from those used in inputting the driving signal from the plurality of signal terminals, the additional signal terminals being provided outside the pixel region; additional connection lines that connect the bus lines to the additional signal terminals; a plurality of switching elements that control connections between the bus lines and the additional connection lines; control signal terminals that are provided outside the pixel region; and control lines that connect the control signal terminals to the plurality of switching elements; wherein the plurality of switching elements are divided into a plurality of groups, and control connections between the plurality of bus lines and the additional connection lines on a group basis, first terminals of the plurality of switching elements are directly connected to the connection lines, second terminals of the plurality of switching elements are directly connected to the additional connection lines, control terminals of the plurality of switching elements are directly connected with the control lines, connection elements that each comprise a diode or a switching element and connect the plurality of signal terminals to each other are provided in the connection terminal region. 2. The active matrix substrate according to claim 1 , wherein the connection elements are each provided between the plurality of signal terminals connected to the bus lines belonging to different groups. 3. The active matrix substrate according to claim 1 , wherein the connection elements are bidirectional diodes, unidirectional diodes or transistors. 4. The active matrix substrate according to claim 1 , wherein each of the plurality of signal terminals is connected to only one adjacent signal terminal through the connection element. 5. The active matrix substrate according to claim 1 , further comprising a short line that connects the pluality of signal terminals and an additional signal terminal that inputs a signal for turning pixels on, wherein the connection elements are provided between the plurality of signal terminals and the short line. 6. The active matrix substrate according to claim 1 , further comprising a plurality of short lines that connect a plurality of sets of the plurality of signal terminals and a plurality of the additional signal terminals, respectively, wherein the connection elements are provided between the signal terminal of the respective sets and the short lines, and each of the sets includes the plurality of signal terminals connected to the switching elements belonging to at least one of the groups. 7. The active matrix substrate according to claim 5 , wherein the connection elements are transistors that control connections between the plurality of signal terminals, and a drain electrode and a source electrode of each transistor are connected to two of the plurality of signal terminals and a gate electrode of each transistor is connected to the short line. 8. The active matrix substrate according to claim 1 , further comprising a shielding film that shields the connection elements from external light. 9. The active matrix substrate according to claim 1 , wherein at least one connection element is provided for every three continuous ones of the plurality of signal terminals, and connects the one of the plurality of signal terminals at a center of the three continuous ones of the plurality of signal terminals to two of the plurality of signal terminals on both sides. 10. A display device comprising the active matrix substrate according to claim 1 .

Assignees

Inventors

Classifications

  • G09G3/006Primary

    Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

  • using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

  • Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title

  • H01L27/156Primary

    Electricity · mapped topic

  • Physics · mapped topic

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What does patent US9614001B2 cover?
An active matrix substrate includes a plurality of bus lines ( 1, 2 ) provided in a pixel region, a plurality of signal terminals ( 5 ) provided in a connection terminal region (K), connection lines ( 3 ), additional signal terminals ( 11 ), test lines ( 8 ), and switching elements ( 4 ). The switching elements ( 4 ) are divided into a plurality of groups, and can control connections between th…
Who is the assignee on this patent?
Kawase Nobuyuki, Ogasawara Isao, Ikuta Kazuhide, and 1 more
What technology area does this patent fall under?
Primary CPC classification G09G3/006. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).