Reducing power for 3D workloads

US10134314B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10134314-B2
Application numberUS-201113976012-A
CountryUS
Kind codeB2
Filing dateNov 30, 2011
Priority dateNov 30, 2011
Publication dateNov 20, 2018
Grant dateNov 20, 2018

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Various embodiments are presented herein that may reduce the workload of a GPU tasked with delivering frames of video data to a display generated by a 3D application executing within a system or computing platform. 3D applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). These frames are then delivered to a display communicatively coupled with the system for rendering. Every display has a refresh rate specified in cycles per second or Hertz (Hz). Vertical Synchronization (VSYNC) is a setting that synchronizes the frames per second (FPS) of a given application with the display's refresh rate. Forcing VSYNC on the application while the system is operating on battery power may reduce the workload on the GPU when the FPS is greater than the refresh rate resulting in greater battery life.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: a processor circuit; and a graphics driver operative on the processor circuit to: execute an application having a three dimensional (3D) workload; determine, prior to enablement of a vertical synchronization (VSYNC) setting, whether a display supports a lower refresh rate than a current refresh rate; instruct the display to operate at the lower refresh rate if the display supports the lower refresh rate; enable the VSYNC setting responsive to the processor circuit operating on battery power and while a percentage level of remaining battery power is lower than a threshold percentage level, the VSYNC setting to enable VSYNC operations to synchronize a frames per second (FPS) specified by the application with the current refresh rate for a display, and enforce the VSYNC setting within the application to synchronize the FPS of the application with the current refresh rate for the display, the graphics driver operative to return VSYNC control to the application when the processor circuit is not operating on battery power. 2. The apparatus of claim 1 , the graphics driver operative to determine when the processor circuit is operating on battery power. 3. The apparatus of claim 2 , the graphics driver operative to determine the threshold percentage level of remaining battery power. 4. The apparatus of claim 1 , the graphics driver operative to override the VSYNC setting within the application to enable the VSYNC operations while the processor circuit is operating on battery power. 5. The apparatus of claim 1 comprising a battery operative to power the processor circuit. 6. The apparatus of claim 1 , the graphics driver operative to lower the refresh rate of the display prior to enabling the VSYNC setting. 7. The apparatus of claim 1 comprising a second processor circuit communicatively coupled to the processor circuit, the second processor circuit operative to present frames for rendering on the display. 8. The apparatus of claim 7 , the processor circuit comprising a central processing unit (CPU), the second processor circuit comprising a graphics processing unit (GPU), and further comprising a display communicatively coupled with the GPU. 9. A method, comprising: executing an application having a 3D workload on a central processing unit (CPU); determining, prior to enablement of a vertical synchronization (VSYNC) setting, whether a display supports a lower refresh rate than a current refresh rate; instructing the display to operate at the lower refresh rate if the display supports the lower refresh rate; enabling the VSYNC setting responsive to the CPU operating on battery power and while a percentage level of remaining battery power is lower than a threshold percentage level, the VSYNC setting enabling VSYNC operations to synchronize a frames per second (FPS) specified by the application with the current refresh rate for a display, enabling the VSYNC operations comprising enforcing a VSYNC setting within the application to synchronize the FPS specified by the application with the current refresh rate for the display, returning VSYNC control to the application when the CPU is not operating on battery power; executing VSYNC operations on a graphics processing unit (GPU); and presenting frames for rendering to the display. 10. The method of claim 9 , comprising: determining the percentage level of remaining battery power while the CPU is operating on battery power. 11. The method of claim 9 , comprising: overriding the VSYNC setting within the application to enable the VSYNC operations when the CPU is operating on battery power. 12. The method of claim 9 , comprising: lowering the refresh rate of the display prior to executing the VSYNC operations. 13. An article of manufacture comprising a non-transitory computer-readable storage medium containing instructions that when executed cause a system to: execute an application having a 3D workload on a central processing unit (CPU); determine, prior to enablement of a vertical synchronization (VSYNC) setting, whether a display supports a lower refresh rate than a current refresh rate; instruct the display to operate at the lower refresh rate if the display supports the lower refresh rate; enable the VSYNC setting responsive to the CPU operating on battery power and while a percentage level of remaining battery power is lower than a threshold percentage level, the VSYNC setting enabling VSYNC operations to synchronize a frames per second (FPS) specified by the application with the current refresh rate for the display, return VSYNC control to the application when the system is not operating on battery power; execute the VSYNC operations on a graphics processing unit (GPU); and present frames for rendering to the display. 14. The article of claim 13 containing instructions that when executed cause a system to: determine the percentage level of remaining battery power while the CPU is operating on battery power. 15. The article of claim 13 containing instructions that when executed cause a system to: override the VSYNC setting within the application to enable the VSYNC function while the system is operating on battery power. 16. The article of claim 13 containing instructions that when executed cause a system to: lower the refresh rate of the display prior to executing the VSYNC function.

Assignees

Inventors

Classifications

  • G09G3/001Primary

    using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background (slide projectors per se G03B23/00 = 42 HP) · CPC title

  • Power saving in display device · CPC title

  • G06F1/3212Primary

    Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title

  • Cross-Sectional Technologies · mapped topic

  • Cross-Sectional Technologies · mapped topic

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Frequently asked questions

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What does patent US10134314B2 cover?
Various embodiments are presented herein that may reduce the workload of a GPU tasked with delivering frames of video data to a display generated by a 3D application executing within a system or computing platform. 3D applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). These frames are then delivered to a …
Who is the assignee on this patent?
Apodaca Michael, Intel Corp
What technology area does this patent fall under?
Primary CPC classification G09G3/001. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 20 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).