Back side via vertical output couplers

Patent metadata

Field	Value
Publication number	US-10132996-B2
Application number	US-201615133920-A
Country	US
Kind code	B2
Filing date	Apr 20, 2016
Priority date	Apr 20, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A method forms a vertical output coupler for a waveguide, formed of waveguide material and disposed within a layer stack on a top surface of a wafer. The method includes etching through a portion of the wafer to form a via that exposes the waveguide material, and etching the waveguide material to remove at least a first portion of the waveguide. The etching forms a tilted plane in the waveguide material. The method further includes coating the first tilted plane with one or more reflective layers, to form a tilted mirror in contact with the first tilted plane in the waveguide material. The tilted mirror forms the vertical output coupler such that light propagating through the waveguide is deflected by the tilted mirror, and exits the waveguide.

First claim

What is claimed is:

1. A method of forming a vertical output coupler for a waveguide, the waveguide being formed of a waveguide material that is disposed within a layer stack on a front surface of a wafer, wherein the layer stack includes a cladding layer atop the waveguide, the method comprising:
defining a via photoresist mask on a back surface of the wafer, wherein:
the via photoresist mask exposes a via shape on the back surface of the wafer and protects other surfaces of the back surface of the wafer, and
etching through a portion of the wafer where the via shape is exposed, to form a via that exposes the waveguide material;

etching the waveguide material to remove at least a first portion of the waveguide, wherein etching the waveguide material forms at least a first tilted plane in the waveguide material;
removing the via photoresist mask;
coating the first tilted plane with one or more reflective layers, to form a tilted mirror in contact with the first tilted plane in the waveguide material;
etching a recess in the cladding layer to expose the waveguide before forming the antireflective coating; and
forming an antireflective coating on the front surface of the wafer such that the light deflected by the tilted mirror passes through the antireflective coating;
wherein the tilted mirror forms the vertical output coupler such that light propagating through the waveguide is deflected by the tilted mirror, exiting the waveguide;
and wherein defining the photoresist mask comprises registering the via shape with the recess so that when etched, the tilted mirror forms within lateral and horizontal bounds of the recess.

2. The method of claim 1 , further comprising:
depositing a top side protective layer over the antireflective coating; and
removing the top side protective layer within at least part of the recess, so as to expose the antireflective coating.

3. The method of claim 1 , wherein the one or more reflective layers include a liner comprising at least one of tantalum and tantalum nitride.

4. The method of claim 1 , further comprising depositing a back side protective layer on the back surface of the wafer, and wherein etching through the portion of the wafer where the via shape is exposed comprises etching through the back side protective layer.

5. The method of claim 1 , wherein a plurality of waveguides are formed of the waveguide material, and wherein two or more of the plurality of waveguides intersect the via so as to form two or more vertical couplers.

6. The method of claim 1 , wherein the one or more reflective layers include a filler comprising at least one of copper and aluminum.

7. The method of claim 6 , wherein the filler substantially fills the via.

8. The method of claim 1 , further comprising forming the waveguide by photolithography and etching of the waveguide material.

9. The method of claim 8 , wherein the photolithography and etching that form the waveguide are repeated, and wherein one instance of the etching does not completely clear the waveguide material, so as to leave a partial thickness shoulder of the waveguide material within an area of the wafer where the via will be formed.

10. The method of claim 9 , wherein the partial thickness shoulder comprises a thickness of the waveguide material within the range of 100 Å to 3000 Å.

11. A method of forming a waveguide with a vertical output coupler, the method comprising:
generating a layer stack on a front surface of a wafer, a back surface of the wafer being opposite the front surface, wherein the layer stack includes:
a first cladding layer,
a crystalline waveguide layer, and
a second cladding layer,
wherein the first cladding layer is disposed nearest a substrate of the wafer, the second cladding layer is disposed furthest from the substrate and the crystalline waveguide layer is disposed between and in contact with both the first cladding layer and the second cladding layer;

forming the waveguide by:
using photolithography and etching on the front surface to form a shoulder region in the crystalline waveguide layer,
using photolithography on the front surface to define a ridge within the shoulder region,
partially etching the shoulder region of the crystalline waveguide layer except where the ridge is defined, and
depositing a second cladding layer over the ridge and the partially etched shoulder region;

using photolithography and etching on the front surface to form a recess region in the second cladding layer, wherein the second cladding layer is removed from at least the ridge within the recess region;
depositing an antireflective coating on the front surface of the wafer such that the antireflective coating is adjacent to and in contact with the ridge within the recess region;
depositing a top side protective layer over the antireflective coating;
removing the top side protective layer within at least part of the recess region, so as to expose the antireflective coating;
defining a via shape in a photoresist mask on the back surface of the wafer, wherein the via shape defined by the photoresist mask is registered with respect to features on the front surface, wherein:
the photoresist mask exposes the via shape on the back surface of the wafer and protects other surfaces of the back surface of the wafer, and
the via shape is vertically aligned, through the wafer, with the recess region;

etching through the substrate and the first cladding layer where the via shape is exposed, to form a via that exposes the waveguide material;
etching the waveguide material to remove at least a first portion of the waveguide, using an etchant that forms at least a first tilted plane in the crystalline waveguide layer;
removing the via photoresist mask; and
coating the first tilted plane with one or more reflective layers, to form a tilted mirror in contact with the first tilted plane in the waveguide material,
wherein the tilted mirror forms the vertical output coupler such that light propagating through the waveguide is deflected by the tilted mirror, and exits the waveguide through the antireflective layer.

12. The method of claim 11 , wherein the one or more reflective layers include a liner comprising at least one of tantalum and tantalum nitride.

13. The method of claim 11 , further comprising depositing a back side protective layer on the back surface of the wafer, and wherein etching through the substrate and the first cladding layer where the via shape is exposed comprises etching through the back side protective layer.

14. The method of claim 11 , wherein forming the waveguide comprises forming a plurality of waveguides from the crystalline waveguide layer, and wherein two or more of the plurality of waveguides intersect the via so as to form two or more vertical couplers.

15. The method of claim 11 , wherein partially etching the shoulder region of the crystalline waveguide layer except where the ridge is defined comprises stopping the etching when the shoulder region reaches a remaining thickness within the range of 100 Å to 3000 Å.

16. The method of claim 11 , wherein the one or more reflective layers include a filler comprising at least one of copper and aluminum.

17. The method of claim 16 , wherein the filler substantially fills the via.

Assignees

• Skorpios Tech Inc

Inventors

• Lambert Damien

Classifications

• G02B2006/12097

  Ridge, rib or the like · CPC title

• G02B6/132

  by deposition of thin films · CPC title

• G02B2006/12061

  Silicon · CPC title

• G02B2006/12169

  Annealing · CPC title

• G02B6/136 Primary

  by etching · CPC title