Magnetic memory device

Patent metadata

Field	Value
Publication number	US-10128311-B2
Application number	US-201715691469-A
Country	US
Kind code	B2
Filing date	Aug 30, 2017
Priority date	Mar 17, 2017
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

According to one embodiment, a magnetic memory device includes a memory cell array unit including magnetoresistive elements provided in an array in first and second directions, each including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first and second magnetic layers, first transistors provided in an array in the first and second directions, and electrically connected to the magnetoresistive elements, respectively, switching units each electrically connected to corresponding ones of the first transistors in series, and each including at least one second transistor, wherein the first magnetic layers are separated from each other in the first and second directions, and the second magnetic layers are continuously provided in the first and second directions.

First claim

What is claimed is:

1. A magnetic memory device comprising a memory cell array unit,
the memory cell array unit comprising:
a plurality of magnetoresistive elements provided in an array form in a first direction and a second direction, each of the magnetoresistive elements including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer;
a plurality of first transistors provided in an array form in the first direction and the second director, and electrically connected to the magnetoresistive elements, respectively;
a plurality of first word lines each extending in the first direction, and each selecting corresponding first transistors from the plurality of first transistors;
a plurality of switching units each electrically connected to corresponding first transistors of the plurality of first transistors in series, and each including at least one second transistor; and
a plurality of second word lines each extending in the second direction, and each selecting a corresponding switching unit from the plurality of switching units, wherein
the first magnetic layers included in the magnetoresistive elements are separated from each other in the first and second directions, and
the second magnetic layers included in the magnetoresistive elements are continuously provided in the first and second directions.

2. The magnetic memory device of claim 1 , wherein
the nonmagnetic layers included in the magnetoresistive elements are continuously provided in the first and second directions.

3. The magnetic memory device of claim 1 , wherein
the nonmagnetic layers included in the magnetoresistive elements are separated from each other in the first and second directions.

4. The magnetic memory device of claim 1 , wherein
each of the magnetoresistive elements further includes a third magnetic layer having a magnetization direction anti-parallel to the magnetization direction of the second magnetic layer, and
the second magnetic layer is provided between the third magnetic layer and the nonmagnetic layer.

5. The magnetic memory device of claim 4 , wherein
the third magnetic layers included in the magnetoresistive elements are continuously provided in the first and second directions.

6. The magnetic memory device of claim 1 , wherein
the memory cell array unit further includes a first plate electrode electrically connected to the magnetoresistive elements and continuously provided in the first and second directions.

7. The magnetic memory device of claim 1 , wherein
the memory cell array unit further includes a second plate electrode electrically connected to the switching units and continuously provided in the first and second directions.

8. The magnetic memory device of claim 1 , wherein
each of the switching units includes a single second transistor electrically connected to corresponding first transistors of the plurality of first transistors in series.

9. The magnetic memory device of claim 1 , wherein
each of the switching units includes a plurality of second transistors each electrically connected to a corresponding first transistor of the plurality of first transistors in series.

10. The magnetic memory device of claim 1 , wherein
each of the first transistors includes a semiconductor portion having a channel length direction perpendicular to the first direction and the second direction, a gate electrode which surrounds the semiconductor portion, and a gate insulating layer provided between the semiconductor portion and the gate electrode.

11. The magnetic memory device of claim 1 , wherein
the at least one second transistor each includes a semiconductor portion having a channel length direction perpendicular to the first direction and the second direction, a gate electrode which surrounds the semiconductor portion, and a gate insulating layer provided between the semiconductor portion and the gate electrode.

12. The magnetic memory device of claim 1 , wherein
a layer including the first transistors is located between a layer including the magnetoresistive elements and a layer including the switching units.

13. The magnetic memory device of claim 1 , wherein
a layer including the first transistors and a layer including the switching units are provided between a layer including the magnetoresistive elements and a semiconductor substrate.

14. The magnetic memory device of claim 1 , wherein
a layer including the magnetoresistive elements is provided between a layer including the first transistors and a semiconductor substrate.

15. The magnetic memory device of claim 1 , wherein
the memory cell array unit further includes a peripheral circuit provided between a semiconductor substrate and an area including the magnetoresistive elements, the first transistors and the switching units.

16. The magnetic memory device of claim 1 , wherein
the memory cell array unit further includes first and second magnetic shield layers such that the magnetoresistive elements, the first transistors and the switching units are interposed between the first and second magnetic shield layers.

17. The magnetic memory device of claim 1 , wherein
the second magnetic layers included in the magnetoresistive elements also function as a plate electrode.

18. The magnetic memory device of claim 1 , wherein
the second direction is perpendicular to the first direction.

19. The magnetic memory device of claim 1 , wherein
the magnetic memory device comprises a plurality of the memory cell array units.

20. The magnetic memory device of claim 19 , further comprising a plurality of sense amplifiers connected to the memory cell array units, respectively.

Assignees

• Toshiba Memory Corp

Inventors

• Ito Yuichi

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H01L27/228 Primary

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title