Magnetoresistive memory device

Patent metadata

Field	Value
Publication number	US-2016379701-A1
Application number	US-201615257085-A
Country	US
Kind code	A1
Filing date	Sep 6, 2016
Priority date	Mar 6, 2014
Publication date	Dec 29, 2016
Grant date	—

Abstract

According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.

First claim

What is claimed is:

1 . A magnetoresistive memory device comprising:
a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance, a first column of memory elements lined up along the first direction being different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.

2 . A magnetoresistive memory device comprising:
a substrate having a first surface; and memory elements each having a switchable resistance, the memory elements positioned at vertexes and center of a right hexagon along the first surface of the substrate.

3 . The device of claim 1 , further comprising:
a first interconnect extending along the first direction.

4 . The device of claim 3 , wherein
the first interconnect extends between the first column of memory elements and the second column of memory element in the first surface.

5 . The device of claim 4 , further comprising:
a first plug provided between the first interconnect and a first memory element of the memory elements in a second direction which intersects the first surface, extending along a third direction which intersects the first direction along the first surface, and overlapping the first interconnect and the first memory element along the first surface.

6 . The device of claim 5 , further comprising:
a second interconnect extending along the first direction; and a second plug between the second interconnect and the substrate in the second direction, wherein the second plug is located on an extension along the third direction from a position between two of the memory elements adjacent in the first direction.

7 . The device of claim 6 , further comprising:
a third interconnect extending along the third direction.

8 . The device of claim 7 , further comprising:
a pair of diffusion areas formed at both sides of the third interconnect in the surface of the substrate, respectively, and wherein the pair of diffusion areas is electrically coupled to one of the memory elements and the second plug, respectively.

9 . The device of claim 1 , further comprising:
a first interconnect extending along a second direction connecting a first memory element in the first column of memory elements and a second memory element in the second column of memory elements nearest to the first memory element.

10 . The device of claim 9 , further comprising:
a second interconnect extending along the first direction, wherein the second interconnect is electrically coupled to two of the memory elements which adjoin in the first direction.

11 . The device of claim 10 , further comprising:
a third interconnect extending along the first direction; and a plug located between the third interconnect and the substrate in a third direction which intersects the first surface, wherein the plug is located on an extension along a fourth direction from a position between two of the memory elements adjacent in the first direction, and the fourth direction intersects the first direction along the first surface.

12 . The device of claim 11 , further comprising:
a pair of diffusion areas formed at both sides of the first interconnect in the surface of the substrate, respectively, wherein the pair of diffusion areas is electrically coupled to one of the memory elements and the plug.

13 . The device of claim 12 , further comprising:
third interconnects comprising the third interconnect and extending along the first direction, and plugs comprising the plug and lined up along the second direction.

14 . A magnetoresistive memory device comprising:
a substrate; an array of memory elements each having a switchable resistance; first interconnects extending from the array of memory elements and coupled to the memory elements; an active area in the surface of the substrate; a plug between one of the first interconnects and the active area; second interconnects adjacent the plug and extending along the surface of the substrate, the array of memory elements being located on extensions of the second interconnects.

15 . The device of claim 14 , wherein
the first interconnects extend along the first direction and lined up along the second direction, the magnetoresistive memory device comprises a cell array area including the array of memory elements, and a first area including the active area and the first interconnects, the first interconnects extending into the first area, a boundary between the cell array area and the first area extends along a third direction which is not perpendicular or parallel to any of the first direction and the second direction.

16 . The device of claim 15 , wherein
a straight line connecting ends of the first interconnects extends along the boundary.

17 . The device of claim 16 , further comprising:
third interconnects extending along the third direction in the cell array area.

18 . The device of claim 17 , wherein
the memory elements are located at vertexes and center of a right hexagon along a first surface of the substrate.

19 . The device of claim 18 , wherein
the third direction extends along a diagonal of the right hexagon.

20 . The device of claim 19 , wherein
the cell array region has a parallelogram shape including a first edge facing the first area and a second edge parallel to the first edge.

21 . The device of claim 1 , further comprising:
an active area extending in the surface of the substrate along the first surface; a first gate electrode and a second gate electrode which extend through the active area; a first plug between one of two sections of the active area outside the first and second gate electrodes, and a first memory element of the memory elements; a second plug between the other one of the two sections of the active area, and a second memory element of the memory elements; a first interconnect; and a third plug between a section of the active area between the first and second electrodes, and the first interconnect.

22 . The device of claim 21 , wherein
the first interconnect extends along the first direction, the first and second gate electrodes extend along a second direction which intersects the first direction along the first surface, and the active area extends along a direction which is not perpendicular or parallel to the first direction along the first surface.

23 . The device of claim 22 , further comprising:
a second interconnect extending along the first direction; a third plug between the first memory element and the second interconnect; and a fourth plug between the second memory element and the second interconnect.

24 . The device of claim 23 , further comprising:
a first conductive layer between the first memory element and the first plug; and a second conductive layer between the second memory element and the second plug.

25 . The device of claim 23 , further comprising:
a first conductive layer between the first memory element and the third plug; and a second conductive layer between the second memory element and the fourth plug.

26 . The device of claim 25 , further comprising:
a third conductive layer between the first memory element and the first conductive layer; and a fourth conductive layer between the second memory element and the second conduc

Assignees

• Toshiba Kk

Inventors

• Nakatsuka Keisuke
• Miyakawa Tadashi
• Hoya Katsuhiko
• Hamamoto Takeshi
• Takenaka Hiroyuki

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C2213/82

  Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/1653

  Address circuits or decoders · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title