Semiconductor integrated circuit structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-10128251-B2
Application number	US-201615261845-A
Country	US
Kind code	B2
Filing date	Sep 9, 2016
Priority date	Sep 9, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

First claim

What is claimed is:

1. A method for forming a semiconductor integrated circuit (IC) structure, comprising:
providing a substrate comprising a memory cell region and a peripheral region defined thereon, and a plurality of memory cells being formed in the memory cell region;
forming a first semiconductor layer in the peripheral region and an insulating layer covering the first semiconductor layer on the substrate;
forming a second semiconductor layer on the substrate, the second semiconductor layer covering the substrate, the first semiconductor layer and the insulating layer;
performing a two-stepped planarization process to remove a portion of the second semiconductor layer and the insulating layer to expose the first semiconductor layer, and a top surface of the first semiconductor layer and a top surface of the second semiconductor layer being coplanar; and
patterning the second semiconductor layer to form a plurality of contact plugs and at least a bit line in the memory cell region and patterning the first semiconductor layer to form at least a gate electrode in the peripheral region.

2. The method for forming the semiconductor IC structure according to claim 1 , further comprising forming a plurality of recesses in the memory cell region, and the substrate being exposed at bottoms of the recesses.

3. The method for forming the semiconductor IC structure according to claim 2 , wherein the second semiconductor layer contacts the substrate exposed at the bottoms of the recesses.

4. The method for forming the semiconductor IC structure according to claim 1 , wherein the first semiconductor layer and the second semiconductor layer comprise a same material.

5. The method for forming the semiconductor IC structure according to claim 1 , wherein a thickness of the insulating layer is larger than 80 angstroms (Å).

6. The method for forming the semiconductor IC structure according to claim 1 , wherein the two-stepped planarization process comprises:
performing a first planarization step to remove a portion of the second semiconductor layer such that the top surface of the second semiconductor layer and a top surface of the insulating layer being coplanar; and
performing a second planarization step to remove a portion of the second semiconductor layer and the insulating layer such that the top surface of the first semiconductor layer and the top surface of the second semiconductor layer being coplanar.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Li Yu-Ting
• Lin Jen-Chieh
• Lin Wen-Chin
• Huang Po-Cheng
• Tsai Fu-Shou

Classifications

• H01L27/10894

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic

• H01L27/10888 Primary

  Electricity · mapped topic

• H01L27/10823

  Electricity · mapped topic

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title