Conductive pillar structure

Patent metadata

Field	Value
Publication number	US-10128206-B2
Application number	US-90450610-A
Country	US
Kind code	B2
Filing date	Oct 14, 2010
Priority date	Oct 14, 2010
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a contact pad over the substrate;
a passivation layer extending over the substrate and having an opening over the contact pad;
an under-bump metallurgy (UBM) layer over the contact pad; and
a conductive pillar over the opening of the passivation layer, wherein a bottom-most surface of the conductive pillar is completely above an upper-most surface of the UBM layer, a lowest portion of the conductive pillar has curved sidewalls, the lowest portion is above a top surface of the passivation layer, and the conductive pillar comprises copper.

2. The semiconductor device of claim 1 wherein the under-bump-metallurgy (UBM) layer is between the contact pad and conductive pillar.

3. The semiconductor device of claim 2 , wherein the under-bump-metallurgy (UBM) layer comprises
a first under-bump-metallurgy (UBM) sub-layer having a first width over the contact pad; and
a second under-bump-metallurgy (UBM) sub-layer having a second width over the first under-bump-metallurgy (UBM) sub-layer, wherein the second width is less than the first width.

4. The semiconductor device of claim 3 , wherein a difference between the first width and second width is in the range of about 0.5 to 10 μm.

5. The semiconductor device of claim 3 , wherein a ratio of the first width to the second width is from about 1.01 to 1.20.

6. The semiconductor device of claim 3 , wherein a thickness of the second under-bump-metallurgy (UBM) sub-layer is in the range of about 4000 and 6000 angstroms.

7. The semiconductor device of claim 3 , wherein a ratio of a thickness of the first under-bump-metallurgy (UBM) sub-layer to a thickness of the second under-bump-metallurgy (UBM) sub-layer is from about 0.15 to 0.25.

8. The semiconductor device of claim 3 , wherein the upper portion of the conductive pillar has an outer edge substantially aligned with an outer edge of the first under-bump-metallurgy (UBM) sub-layer.

9. The semiconductor device of claim 3 , wherein an outer edge of the second under-bump-metallurgy (UBM) sub-layer is substantially aligned with an inner edge of the lowest portion of the conductive pillar.

10. The semiconductor device of claim 3 , wherein an outer edge of the second under-bump-metallurgy (UBM) sub-layer is between an outer edge of the lowest portion of the conductive pillar and an inner edge of the lowest portion of the conductive pillar.

11. The semiconductor device of claim 3 , wherein the conductive pillar and the second under-bump-metallurgy (UBM) layer comprise the same material.

12. A semiconductor device comprising:
a substrate;
an inter-metal dielectric (IMD) layer over the substrate, the IMD layer having a top conductive layer;
an under bump metallurgy (UBM) layer electrically connected to the top conductive layer; and
a conductive pillar over the UBM layer, wherein sidewalls of the conductive pillar extending from a top portion to a bottom portion are perpendicular to a top surface of the substrate and a lowest portion of the conductive pillar having curved sidewalls, the lowest portion disposed over an uppermost surface of the UBM layer, and the conductive pillar comprises copper.

13. The semiconductor device of claim 12 , wherein an outer surface of the lowest portion of the conductive pillar and a top surface of the UBM layer form an acute angle.

14. The semiconductor device of claim 12 , further comprising a passivation layer formed between the UBM layer and the top conductive layer, the passivation layer defining an opening, the UBM layer is electrically connected to the top conductive layer in the opening.

15. The semiconductor device of claim 14 , wherein a width of the opening is less than a width of the lowest portion of the conductive pillar.

16. The semiconductor device of claim 12 , wherein the UBM layer comprises
a first UBM layer having a first width; and
a second UBM layer over the first UBM layer, the second UBM layer having a second width less than the first width.

17. An integrated circuit comprising:
a substrate having a plurality of microelectronic elements formed therein;
a contact pad over the substrate;
a under-bump-metallurgy (UBM) layer over the contact pad;
a passivation layer extending over the substrate and having an opening over the contact pad; and
a conductive pillar over the opening of the passivation layer, wherein a lowest portion of the conductive pillar has curved sidewalls, the lowest portion is above a top surface of the passivation layer, an entirety of a sidewall extending from a bottom-most surface of the conductive pillar to an upper-most surface of the conductive pillar is free from contact with the UBM layer, and the conductive pillar comprises copper.

18. The integrated circuit of claim 17 , wherein the UBM layer comprises:
a first under-bump-metallurgy (UBM) layer having a first width over the contact pad; and
a second UBM layer having a second width over the first UBM layer, wherein the second width is less than the first width.

19. The integrated circuit of claim 18 , wherein an outer edge of the second UBM layer is substantially aligned with an inner edge of the lowest portion of the conductive pillar.

20. The integrated circuit of claim 18 , wherein an outer edge of the second UBM layer is between an outer edge of the lowest portion of the conductive pillar and an inner edge of the lowest portion of the conductive pillar.

Assignees

• Lin Chih Wei
• Cheng Ming Da
• Lu Wen Hsiung
• Chou Meng Wei
• Kuo Hung Jui
• Liu Chung Shi
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chih-Wei
• Cheng Ming-Da
• Lu Wen-Hsiung
• Chou Meng-Wei
• Kuo Hung-Jui
• Liu Chung-Shi

Classifications

• H10W72/07551

  characterised by changes in properties of the bond wires during the connecting · CPC title

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title