Electronic package and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10128178-B2
Application number	US-201615258441-A
Country	US
Kind code	B2
Filing date	Sep 7, 2016
Priority date	May 18, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.

First claim

What is claimed is:

1. An electronic package, comprising:
a circuit structure having a first surface provided with a first circuit layer and an opposite second surface provided with a second circuit layer;
a metal layer formed on the first surface of the circuit structure and electrically connected to the first circuit layer;
an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer;
an encapsulant formed on the first surface of the circuit structure and encapsulating the electronic element;
a plurality of conductive posts disposed on the second surface of the circuit structure and electrically connected to the second circuit layer; and
an insulating layer formed on the second surface of the circuit structure and encapsulating the conductive posts,
wherein a portion of a surface of each of the conductive posts is exposed from the insulating layer; wherein the encapsulant is in contact with the insulating layer.

2. The electronic package of claim 1 , wherein the first circuit layer has a minimum trace width less than a minimum trace width of the second circuit layer.

3. The electronic package of claim 1 , wherein the metal layer is a patterned circuit layer.

4. The electronic package of claim 1 , wherein the encapsulant and the insulating layer are made of the same material.

5. The electronic package of claim 1 , wherein the encapsulant and the insulating layer are made of different materials.

6. The electronic package of claim 1 , wherein the encapsulant extends to a side surface of the circuit structure.

7. The electronic package of claim 1 , further comprising a plurality of conductive elements disposed on the conductive posts.

8. The electronic package of claim 1 , further comprising an electronic component disposed on the conductive posts.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Lu-Yi
• Li Hung-Yuan
• Lai Chieh-Lung
• Peng Shih-Liang
• Lu Chang-Lun

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/0198

  batch processes · CPC title