Dielectric fuse memory circuit and operation method thereof

Patent metadata

Field	Value
Publication number	US-10127993-B2
Application number	US-201615222983-A
Country	US
Kind code	B2
Filing date	Jul 29, 2016
Priority date	Jul 29, 2015
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

One time programming and repeatably random read integrated circuit memory has a storage device that programs the information by using dielectric-fuse mechanism. The main characteristics of dielectric fuse mechanisms is that by applying an electric field on the dielectrics, the ions or atoms in the dielectrics are drifted-out, or the dielectrics are burned-out, that create damage of the dielectric structure in a form of porosity, and the conductivity (resistivity) of tunneling current through the dielectrics changes the state from high conductivity (resistivity) to low conductivity (resistivity). The dielectric fuse mechanism has been integrated in VLSI circuits, completed the validation, and implemented by the fabrication of CMOS process.

First claim

What is claimed is:

1. An integrated circuit memory, comprising:
plural memory cells, wherein each of the memory cells is connected to at least one decoding line or at least one ground line, and each of the memory cells comprises:
a first field-effect transistor, comprising:
a first region, a second region and a third region, wherein the third region is connected to the first region and the second region;
at least one gate dielectric layer being disposed on the third region; and
at least one gate electrode layer being configured to receive and apply a first electric signal to the gate dielectric layer, such that the first electric signal renders the conduction of an electric signal between the first region and the second region through the third region; and

a second field-effect transistor, comprising:
a first region, a second region and a third region, wherein the third region is connected to the first region and the second region;
at least one gate dielectric layer being disposed on the third region; and
at least one gate electrode layer being configured to receive and apply a second electric signal to the gate dielectric layer;
wherein applying the second electric signal to the gate dielectric layer of the second field-effect transistor renders the conductivity of the gate dielectric layer from high state to low state, and the conductivity of the gate dielectric layer is not changed by applying the second electric signal to the gate dielectric layer of the second field-effect transistor again, wherein the high state and the low state of the gate dielectric layer respectively represent two different storing states of the memory cell,
wherein the second electric signal is larger than a hard breakdown voltage of the second field-effect transistor.

2. The integrated circuit memory of claim 1 , wherein at least one gate electrode layer of the second field-effect transistor is connected to a first decoding line, and the first region of the second field-effect transistor is connected to or shared with the second region of the first field-effect transistor.

3. The integrated circuit memory of claim 2 , wherein the second region of the second field-effect transistor is connected to a fourth decoding line.

4. The integrated circuit memory of claim 2 , wherein the gate electrode layer of the first field-effect transistor is connected to a second decoding line, and the first region of the first field-effect transistor is connected to a third decoding line, wherein each of the first field-effect transistor and the second field-effect transistor comprises a ground terminal, and the ground terminal is connected to the ground line of the memory cell.

5. The integrated circuit memory of claim 4 , wherein the first field-effect transistors of two adjacent memory cells of the memory cells are connected to the third decoding line.

6. The integrated circuit memory of claim 1 , wherein when the gate dielectric layer of the second field-effect transistor comprises one dielectric layer, the relative permittivity of the dielectric layer is less than or equal to 10; when the gate dielectric layer of the second field-effect transistor comprises plural dielectric layers, the relative permittivity of one of the dielectric layers is less than or equal to 10, and the relative permittivities of the other the dielectric layers are larger than the relative permittivities of the one dielectric layer.

7. The integrated circuit memory of claim 5 , wherein applying decoding electric signals to the first decoding line, the second decoding line and the third decoding line renders the first field-effect transistor of one of the memory cells conductive, such that a voltage difference or a current is generated at two terminals of a gate oxide layer of the second field-effect transistor, so as to change the conductivity of the gate dielectric layer of the second field-effect transistor from high state to low state for storing information.

8. The integrated circuit memory of claim 7 , wherein applying the decoding electric signals to the first decoding line, the second decoding line and the third decoding line renders the first field-effect transistor of one of the memory cells conductive, and the intensity of the decoding electric signals is sensed from the first decoding line or the third decoding line which is read as the state of the conductivity of the gate dielectric layer of the second field-effect transistor.

9. The integrated circuit memory of claim 5 , wherein applying decoding electric signals to the first decoding line and a fourth decoding line renders a voltage difference is generated at two terminals of the gate dielectric layer of the second field-effect transistor, so as to change the conductivity of the gate dielectric layer of the second field-effect transistor from high state to low state, the conductivity of the gate dielectric layer of the second field-effect transistor is therefore changed for storing information.

10. The integrated circuit memory of claim 9 , wherein applying the decoding electric signals to the second decoding line and the third decoding line renders the first field-effect transistor of one of the memory cells conductive, applying the decoding electric signals around reference ground to the first decoding line and the fourth decoding line, and the intensity of the decoding electric signals is sensed from the third decoding line or the fourth decoding line which is read as the state of the conductivity of the gate dielectric layer of the second field-effect transistor.

11. An integrated circuit memory, comprising:
plural memory cells, wherein each of the memory cells is connected to at least one decoding line or at least one ground line, and each of the memory cells comprises:
a field-effect transistor, comprising:
a first region, a second region and a third region, wherein the third region is connected to the first region and the second region;
at least one gate dielectric layer being disposed on the third region; and
at least one gate electrode layer being configured to receive and apply a first electric signal to the gate dielectric layer, such that the first electric signal renders the conduction of an electric signal between the first region and the second region through the third region; and

a storing component, comprising:
at least one dielectric layer, applying the second electric signal to at least one dielectric layer of the storing component renders the conductivity of the at least one dielectric layer from high state to low state for writing information into the storing component, wherein the conductivity of the at least one dielectric layer is not changed by applying the second electric signal to the at least one dielectric layer of the storing component again, wherein the high state and the low state of the dielectric layer respectively represent two different storing states of the memory cell,
wherein the second electric signal is larger than a hard breakdown voltage of the storing component.

12. The integrated circuit memory of claim 11 , wherein the storing component further comprises:
a first layer portion, wherein the at least one dielectric layer of the storing component is disposed on the first layer portion; and
a second layer portion being disposed on the at least one dielectric layer;
wherein the first layer portion is a first electrode or a first interconnect, and the second layer portion is a second electrode or a second interconnect.

13. The integrated circuit memory of claim 12 , wherein the first electrode, the second electrode, the first interconnect and the second interconnect are selected from the group co

Assignees

• Univ National Chiao Tung

Inventors

• Chung Steve S
• Hsieh E-Ray
• Huang zhi-hong

Classifications

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H01L27/11206

  Electricity · mapped topic

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• H01L23/5256

  Electricity · mapped topic

• G11C17/16

  using electrically-fusible links · CPC title