Low overheard high throughput solution for point-to-point link

Patent metadata

Field	Value
Publication number	US-10127184-B2
Application number	US-201615277893-A
Country	US
Kind code	B2
Filing date	Sep 27, 2016
Priority date	Sep 27, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support communication with a level of a multi-level system memory. The point-to-point link interface circuit includes a circuit to interlace payload data with cyclic redundancy check (CRC) values, where, different data segments of the payload are each appended with its own respective CRC value.

First claim

The invention claimed is:

1. An apparatus, comprising:
a point-to-point link interface circuit, the point-to-point link interface circuit to support communication with a level of a multi-level system memory, the point-to-point link interface circuit comprising a circuit to, in order to reduce propagation delay of a packet, interlace payload data of the packet with cyclic redundancy check (CRC) values of the packet, where, different data segments of the payload are each appended with its own respective CRC value.

2. The apparatus of claim 1 wherein the point-to-point link interface circuit comprises a Peripheral Component Interconnect Express (PCIe) compliant interface.

3. The apparatus of claim 1 wherein an LCRC field of a PCIe packet structure is not utilized.

4. The apparatus of claim 1 wherein the point-to-point link interface circuit is disposed on a main memory controller that is to interface to the multi-level system memory.

5. The apparatus of claim 1 wherein the point-to-point link interface circuit is disposed on a controller that is to reside between a main memory controller that is to interface with the multi-level system memory and emerging non volatile system memory technology devices.

6. The apparatus of claim 5 wherein the emerging non volatile system memory technology stores data with resistive storage cells.

7. The apparatus of claim 1 wherein the circuit precedes a PCIe transaction layer circuit in the transmit direction.

8. The apparatus of claim 1 wherein the circuit follows a PCIe transaction layer circuit in the receive direction.

9. A computing system, comprising:
a plurality of processing cores;
a multi-level system memory;
main memory controller coupled to the multi-level system memory
a point-to-point link interface circuit, the point-to-point link interface circuit to support communication with a level of a multi-level system memory, the point-to-point link interface circuit comprising a circuit to, in order to reduce propagation delay of a packet, interlace payload data of the packet with cyclic redundancy check (CRC) values of the packet, where, different data segments of the payload are each appended with its own respective CRC value.

10. The computing system of claim 9 wherein the point-to-point link interface circuit comprises a PCIe compliant interface.

11. The computing system of claim 9 wherein an LCRC field of a PCIe packet structure is not utilized.

12. The computing system of claim 9 wherein the point-to-point link interface circuit is disposed on a main memory controller that is to interface to the multi-level system memory.

13. The computing system of claim 9 wherein the point-to-point link interface circuit is disposed on a controller that is to reside between a main memory controller that is to interface with the multi-level system memory and emerging non volatile system memory technology devices.

14. The computing system of claim 13 wherein the emerging non volatile system memory technology devices comprise chalcogenide.

15. The computing system of claim 9 wherein the circuit precedes a PCIe transaction layer circuit in the transmit direction.

16. The computing system of claim 9 wherein the circuit follows a PCIe transaction layer circuit in the receive direction.

17. A method performed by a point-to-point interface circuit to reduce propagation delay of a packet, comprising:
receiving a payload of random customer data that is to be written into a multi-level system memory or has been read from a multi-level system memory;
calculating respective CRC values from different segments of the random customer data;
appending each of the different data segments of the payload with its respective CRC value to form an expanded payload;
presenting the expanded payload to a point-to-point link transaction layer for transmission of the packet over a point-to-point link.

18. The method of claim 17 wherein the point-to-point link is a PCIe compliant link.

19. The method of claim 17 wherein the method is performed on a main memory controller that interfaces with the multi-level system memory.

20. The method of claim 17 wherein the method is performed on a controller that resides between a main memory controller that interfaces with the multi-level system memory and emerging non volatile memory devices of the multi-level system memory.

Assignees

• Intel Corp

Inventors

• Ooi Eng Hun
• Lim Su Wei

Classifications

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F11/3027

  where the computing system component is a bus · CPC title

• G06F11/349

  for interfaces, buses · CPC title

• G06F11/3051

  Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247) · CPC title