Materials for use with interconnects of electrical devices and related methods

US10123430B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10123430-B2
Application numberUS-87383807-A
CountryUS
Kind codeB2
Filing dateOct 17, 2007
Priority dateOct 17, 2006
Publication dateNov 6, 2018
Grant dateNov 6, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Certain examples disclosed herein are directed to materials that are designed for use in interconnects of electrical devices such as, for example, printed circuit boards and solar cells. In certain examples, a two-step solder may be used to reduce stresses on the materials used in the production of the electrical devices.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of providing an electrical connection in a solar cell assembly comprising a circuit board and a silicon-containing layer, the method comprising: disposing a two-step solder on or between the circuit board and the silicon-containing layer, the two-step solder comprising a low melt solder component disposed on a base solder component; subjecting the low melt solder component to a first processing step of melting the low melt solder component of the two-step solder to form a solder alloy or an intermetallic from the low melt solder component and the base solder component; and thereafter laser soldering the solar cell assembly at an effective temperature to provide an electrical connection between the circuit board and the silicon-containing layer; wherein the solar cell assembly further comprising a backing layer coupled to the circuit board and a protective covering coupled to the silicon-containing layer. 2. The method of claim 1 , in which the effective temperature to melt the low melt solder component of the two-step solder is about 150° C. or less. 3. The method of claim 2 , wherein the effective temperature to solder the alloy or intermetallic layer is at least about 250° C. 4. The method of claim 1 , in which the low melt solder component of the two-step solder is configured as a low melt solder selected from the group consisting of Sn(42)/Bi(58), Sn (30-50)/Bi(70-30), Sn(42)/Bi(57)/Ag(1), Sn(30-50)/Bi(70-30)/Ag(0-5), Sn(50)/In(50), Sn(30-50)/In(70-30), In(97)/Ag(3), In(90-100)/Ag(0-10), Sn(50)/Pb(32)/Cd(18), Sn(30-60)/Pb(20-40)/Cd(10-30), Sn(43)/Pb(43)/Bi(14) and Sn(30-50)/Pb(30-50)/Bi(5-20). 5. The method of claim 4 , in which the base solder component of the two-step solder is selected from the group consisting of Sn(90-100)/Ag(0-5)/Cu(0-5), Sn(96.5)/Ag(3.5), Sn(90-95)/Ag(0-5), Sn(99)/Cu(1), Sn(95-100)/Cu(0-5), Sn(100), Sn(63)/Pb(37), Sn(20-80)/Pb(0-20), Sn(62)/Pb(36)/Ag(2), Sn(50-70)/Pb(30-50)/Ag(0-5), Sn(60)/Pb(38/Cu(2), and Sn(50-70)/Pb(30-50)/Cu(0-5). 6. The method of claim 5 , wherein the base solder component of the two-two solder is about Sn96.5 Ag3.0 Cu0.5 or about Sn99.0 Ag0.3 Cu0.7. 7. The method of claim 1 , in which the two-step solder disposed between the circuit board and the silicon-containing layer is configured as a solder preform. 8. The method of claim 1 , further comprising disposing a sealant between the circuit board and the silicon-containing layer prior to melting the low melt solder component of the two-step solder.

Assignees

Inventors

Classifications

  • Soldering or alloying · CPC title

  • Applying EM radiation, e.g. induction heating or using a laser · CPC title

  • Soldering or alloying · CPC title

  • Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

  • Solder materials or compositions specially adapted therefor · CPC title

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Frequently asked questions

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What does patent US10123430B2 cover?
Certain examples disclosed herein are directed to materials that are designed for use in interconnects of electrical devices such as, for example, printed circuit boards and solar cells. In certain examples, a two-step solder may be used to reduce stresses on the materials used in the production of the electrical devices.
Who is the assignee on this patent?
Marczi Michael T, Koep Paul, De Monchy Michiel A, and 3 more
What technology area does this patent fall under?
Primary CPC classification H05K3/3484. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).