Method and apparatus for performing a holdover function on a holdover line card

Patent metadata

Field	Value
Publication number	US-10122525-B2
Application number	US-201715456211-A
Country	US
Kind code	B2
Filing date	Mar 10, 2017
Priority date	Mar 10, 2017
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Various embodiments relate to a network node and method thereof including a high stability oscillator and a holdover phase-locked loop (“PLL”) wherein the holdover PLL is configured to perform a holdover function by receiving a system clock signal, disciplining the high stability oscillator using the system clock signal to generate a local reference signal, and providing the local reference signal as the system clock signal when the system clock signal becomes unavailable.

First claim

What is claimed is:

1. A network node, comprising:
a timing circuit comprising a phase lock loop (“PLL”) and a first oscillator, wherein the PLL is configured to generate a system clock signal based on source timing information and an output of the first oscillator;
a holdover circuit comprising a second oscillator, the second oscillator having higher stability than the first oscillator, the holdover circuit using the system clock signal from the timing circuit to discipline the second oscillator and generate a local reference clock signal,
wherein the local reference clock signal is used as the source timing information for the timing circuit to generate a disciplined system clock signal in response to which the holdover circuit does not discipline using the disciplined system clock signal.

2. The network node of claim 1 , further comprising:
reverting back to the system clock signal based on source timing information.

3. The network node of claim 1 , wherein the system clock signal is received from a synchronous equipment timing source (“SETS”) PLL on a timing circuit.

4. The network node of claim 3 , wherein the local reference clock signal is provided from the holdover circuit to the timing circuit.

5. The network node of claim 1 , further comprising the holdover circuit:
determining whether the system clock signal has become unavailable.

6. The network node of claim 3 , further comprising the holdover circuit:
locking the SETS PLL on the timing circuit to the local reference clock signal.

7. The network node of claim 3 , wherein the system clock signal is transmitted from a fanout on the timing circuit to the holdover circuit.

8. The network node of claim 3 , wherein the local reference clock signal is transmitted from the holdover circuit to a selector on the timing circuit.

9. The network node of claim 3 , wherein the second oscillator is a temperature-compensated crystal oscillator, an oven controlled crystal oscillator, a double oven controlled crystal oscillator, an atomic clock or any oscillator which has a higher stability than the first oscillator.

10. The network node of claim 3 , wherein the second oscillator is positioned external to the holdover circuit and connected to the holdover circuit to achieve the same effect as if positioned on the holdover circuit.

11. A method for performing a holdover function on a network node, comprising the steps of:
generating a system clock signal, by a phase lock loop (“PLL”) on a timing circuit including and a first oscillator, based on source timing information and an output of the first oscillator;
disciplining, by a holdover circuit including a second oscillator, the second oscillator having higher stability than the first oscillator, the second oscillator using the system clock signal from the timing circuit and generating a local reference clock signal,
wherein the local reference clock signal is used as the source timing information for the timing circuit to generate a disciplined system clock signal in response to which the holdover circuit does not discipline using disciplined the system clock signal.

12. The method of claim 11 , further comprising:
reverting back to the system clock signal based on source timing information.

13. The method of claim 11 , wherein the system clock signal is received from a synchronous equipment timing source (“SETS”) PLL on a timing circuit.

14. The method of claim 13 , wherein the local reference clock signal is provided from the holdover circuit to the timing circuit.

15. The method of claim 11 , further comprising:
determining whether the system clock signal has become unavailable.

16. The method of claim 13 , further comprising:
locking the SETS PLL on the timing circuit to the local reference clock signal.

17. The method of claim 13 , wherein the system clock signal is transmitted from a fanout on the timing circuit to the holdover circuit.

18. The method of claim 13 , wherein the local reference clock signal is transmitted from the holdover circuit to a selector on the timing circuit.

19. The method of claim 13 , wherein the second oscillator is a temperature-compensated crystal oscillator, an oven controlled crystal oscillator, a double oven controlled crystal oscillator, an atomic clock or any oscillator which has a higher stability than the first oscillator.

20. The method of claim 13 , wherein the second oscillator is positioned external to the holdover circuit and connected to the holdover circuit to achieve the same effect as if positioned on the holdover circuit.

Assignees

• Creasy Simon P
• Driediger Steven G
• Nokia America Corp

Inventors

• Creasy Simon P
• Driediger Steven G

Classifications

• H04L5/0048

  Allocation of pilot signals, i.e. of signals known to the receiver (allocation of control signalling H04L5/0053; use of control signalling H04L5/0091) · CPC title

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/143

  by switching the reference signal of the phase-locked loop · CPC title

• H03L7/14

  for assuring constant frequency when supply or correction voltages fail · CPC title

• H03L7/22

  using more than one loop · CPC title